USB control circuit with built-in signal repeater circuit

Patent metadata

Field	Value
Publication number	US-10146728-B2
Application number	US-201615190898-A
Country	US
Kind code	B2
Filing date	Jun 23, 2016
Priority date	Jul 7, 2015
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A USB control circuit of a USB hub device includes: an upstream MAC-layer circuit; a downstream MAC-layer circuit; a first USB PHY-layer circuit; a second USB PHY-layer circuit; a first switch circuit for communicating data with an upstream port through the first USB PHY-layer circuit; a second switch circuit for communicating data with a downstream port through the second USB PHY-layer circuit; a control signal transmission interface; a signal repeater circuit; and a control unit configured to operably control the first switch circuit and the second switch circuit through the control signal transmission interface, so that the first switch circuit selectively couples the upstream MAC-layer circuit or the signal repeater circuit with the first USB PHY-layer circuit, while the second switch circuit selectively couples the downstream MAC-layer circuit or the signal repeater circuit with the second USB PHY-layer circuit.

First claim

What is claimed is:

1. A USB control circuit ( 110 ) of a USB hub device ( 100 ), wherein the USB hub device ( 100 ) comprises an upstream port ( 102 ) and a downstream port ( 104 ), the USB control circuit ( 110 ) comprising:
an upstream MAC-layer circuit ( 111 );
a downstream MAC-layer circuit ( 112 );
a first USB PHY-layer circuit ( 113 );
a second USB PHY-layer circuit ( 114 );
a first switch circuit ( 115 ), arranged to operably communicate data with the upstream port ( 102 ) through the first USB PHY-layer circuit ( 113 );
a second switch circuit ( 116 ), arranged to operably communicate data with the downstream port ( 104 ) through the second USB PHY-layer circuit ( 114 );
a control signal transmission interface ( 117 ), coupled with the first switch circuit ( 115 ) and the second switch circuit ( 116 );
a signal repeater circuit ( 118 ), coupled between the first switch circuit ( 115 ) and the second switch circuit ( 116 ); and
a control unit ( 119 ), coupled with the control signal transmission interface ( 117 ), arranged to operably control the first switch circuit ( 115 ) and the second switch circuit ( 116 ) through the control signal transmission interface ( 117 ), so that the first switch circuit ( 115 ) selectively couples one of the upstream MAC-layer circuit ( 111 ) and the signal repeater circuit ( 118 ) to the first USB PHY-layer circuit ( 113 ) while the second switch circuit ( 116 ) selectively couples one of the downstream MAC-layer circuit ( 112 ) and the signal repeater circuit ( 118 ) to the second USB PHY-layer circuit ( 114 );
wherein when the control unit ( 119 ) controls the first switch circuit ( 115 ) to couple the signal repeater circuit ( 118 ) with the first USB PHY-layer circuit ( 113 ), the control unit ( 119 ) also controls the second switch circuit ( 116 ) to couple the signal repeater circuit ( 118 ) with the second USB PHY-layer circuit ( 114 ), the first switch circuit ( 115 ) is de-coupled from the upstream MAC-layer circuit ( 111 ) and the second switch circuit ( 116 ) is de-coupled from the downstream MAC-layer circuit ( 112 ) such that no signal is transmitted between the first switch circuit ( 115 ) and the upstream MAC-layer circuit ( 111 ) while no signal is transmitted between the second switch circuit ( 116 ) and the downstream MAC-layer circuit ( 112 ).

2. The USB control circuit ( 110 ) of claim 1 , wherein when the upstream port ( 102 ) is connected to an OTG device, the downstream port ( 104 ) is connected to a USB host device, the first switch circuit ( 115 ) couples the signal repeater circuit ( 118 ) with the first USB PHY-layer circuit ( 113 ), and the second switch circuit ( 116 ) couples the signal repeater circuit ( 118 ) with the second USB PHY-layer circuit ( 114 ), the OTG device is enabled to operate as a USB peripheral device to communicate data with the USB host device.

3. The USB control circuit ( 110 ) of claim 1 , wherein when a predetermined command is received by the control unit ( 119 ), the control unit ( 119 ) controls the first switch circuit ( 115 ) to couple the signal repeater circuit ( 118 ) with the first USB PHY-layer circuit ( 113 ) and also controls the second switch circuit ( 116 ) to couple the signal repeater circuit ( 118 ) with the second USB PHY-layer circuit ( 114 ).

4. The USB control circuit ( 110 ) of claim 3 , further comprising:
a command receiving interface ( 120 ), coupled with the control unit ( 119 ), arranged to operably receive the predetermined command from an external circuit and to operably transmit the predetermined command to the control unit ( 119 ).

5. The USB control circuit ( 110 ) of claim 1 , wherein the first switch circuit ( 115 ) or the second switch circuit ( 116 ) is a multiplexer.

6. The USB control circuit ( 110 ) of claim 1 , wherein when the control unit ( 119 ) controls the first switch circuit ( 115 ) to couple the signal repeater circuit ( 118 ) with the first USB PHY-layer circuit ( 113 ) and also controls the second switch circuit ( 116 ) to couple the signal repeater circuit ( 118 ) with the second USB PHY-layer circuit ( 114 ), the upstream port ( 102 ) and the downstream port ( 104 ) transmit signals through the first switch circuit ( 115 ), the signal repeater circuit ( 118 ), and the second switch circuit ( 116 ) without using the upstream MAC-layer circuit ( 111 ) and the downstream MAC-layer circuit ( 112 ) as intermediate circuits.

7. The USB control circuit ( 110 ) of claim 6 , wherein when the control unit ( 119 ) controls the first switch circuit ( 115 ) to couple the signal repeater circuit ( 118 ) with the first USB PHY-layer circuit ( 113 ) and also controls the second switch circuit ( 116 ) to couple the signal repeater circuit ( 118 ) with the second USB PHY-layer circuit ( 114 ), the upstream MAC-layer circuit ( 111 ) and the downstream MAC-layer circuit ( 112 ) are capable of being turned off to reduce power consumption.

Assignees

• Realtek Semiconductor Corp

Inventors

• Liu Chong
• Wang Luo-Bin
• Zeng Jian-Jhong
• Lin Neng-Hsien

Classifications

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• Y02D10/151

  Cross-Sectional Technologies · mapped topic

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title