Method and apparatus for performing logical compare operations

Patent metadata

Field	Value
Publication number	US-10146536-B2
Application number	US-201815885269-A
Country	US
Kind code	B2
Filing date	Jan 31, 2018
Priority date	Sep 21, 2006
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

First claim

What is claimed is:

1. A processor, comprising:
a cache to store instructions;
an instruction decoder to decode the instructions;
a set of 128-bit packed data registers to store packed data elements and packed integer data elements;
an execution unit comprising:
comparison circuitry to execute a packed instruction to:
compare a first packed data element and a second packed data element and to responsively set at least one bit in a register to indicate a result of the packed comparison;
compare a first packed integer data element and a second packed integer data element and to responsively set the at least one bit in the register to indicate a result of the packed integer comparison; and
determine a target code location based on the at least one bit set in the register.

2. The processor of claim 1 wherein the set of 128-bit packed data registers comprises at least one set of physical registers for storing both scalar floating-point values and vector data elements.

3. The processor of claim 1 further comprising:
instruction fetch circuitry to fetch the instructions.

4. The processor of claim 1 further comprising:
a memory interface to couple the processor to a system memory.

5. The processor of claim 1 further comprising:
a co-processor interface to couple the processor to one or more external processors.

6. The processor of claim 1 further comprising:
a data storage interface to couple the processor to a data storage device.

7. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
storing instruction in a cache;
decoding the instructions;
storing packed data elements and packed integer data elements in a set of 128-bit packed data registers;
executing a packed instruction to:
compare a first packed data element and a second packed data element and responsively setting at least one bit in a register to indicate a result of the packed comparison;
compare a first packed integer data element and a second packed integer data element and responsively setting the at least one bit in the register to indicate a result of the packed integer comparison; and
determine a target code location based on the at least one bit set in the register.

8. The non-transitory machine-readable medium of claim 7 wherein the set of 128-bit packed data registers comprises at least one set of physical registers for storing both scalar floating-point values and vector data elements.

9. A method comprising:
storing instruction in a cache;
decoding the instructions;
storing packed data elements and packed integer data elements in a set of 128-bit packed data registers;
executing a packed instruction to:
compare a first packed data element and a second packed data element and responsively setting at least one bit in a register to indicate a result of the packed comparison;
compare a first packed integer data element and a second packed integer data element and responsively setting the at least one bit in the register to indicate a result of the packed integer comparison; and
determine a target code location based on the at least one bit set in the register.

10. The method of claim 9 wherein the set of 128-bit packed data registers comprises at least one set of physical registers for storing both scalar floating-point values and vector data elements.

Assignees

• Intel Corp

Inventors

• Kapoor Rajiv
• Zohar Ronen
• Buxton Mark
• Sperber Zeev
• Gottlieb Koby

Classifications

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/30094

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F7/026

  Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title