Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints

Patent metadata

Field	Value
Publication number	US-10146291-B2
Application number	US-201514757924-A
Country	US
Kind code	B2
Filing date	Dec 24, 2015
Priority date	Mar 15, 2013
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a transmitter to transmit serial data, a receiver to deserialize serial data, and control logic to implement a protocol stack. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device. The protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device. The protocol stack further provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time.

First claim

What is claimed is:

1. A high speed serial point-to-point link interface to enable communication between a processor and a device over a physical channel, the high speed serial point-to-point link interface comprising:
a transmitter to transmit serial data;
a receiver to deserialize serial data; and
control logic to implement a protocol stack, wherein the protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device;
wherein the protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device;
wherein the protocol stack provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time; and
wherein the active state is an uninitialized active state and accessing the device prior to expiration of the default recovery time to complete the transition comprises sending a configuration access request to the device.

2. The serial point-to-point link interface of claim 1 , wherein the protocol stack is a peripheral component interconnect express (PCIe) protocol stack and the device is a PCIe endpoint device.

3. The serial point-to-point link interface of claim 1 , wherein the device-advertised recovery time is specified in a register of the device.

Assignees

• Intel Corp

Inventors

• Wagh Mahesh
• Gough Robert E

Classifications

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3246

  by software initiated power-off · CPC title