Platform communication protocol

Patent metadata

Field	Value
Publication number	US-10146290-B2
Application number	US-201715658337-A
Country	US
Kind code	B2
Filing date	Jul 24, 2017
Priority date	Sep 30, 2008
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

First claim

What is claimed is:

1. An apparatus comprising:
a processor comprising hardware-implemented logic to:
generate a wake message, wherein the wake message comprises a packet to include at least twelve bytes, the packet includes at least one code field to include a particular code defined to indicate that the packet comprises a wake message, and the particular code comprises at least five bits, wherein the packet further comprises an address field, a tag field, a field to identify length of the packet, and an identifier field to identify the source of the packet; and
send the wake message to another device over an interconnect, wherein the wake message is to cause a resource of the other device to be activated.

2. The apparatus of claim 1 , wherein the wake message comprises an in-band wake message.

3. The apparatus of claim 1 , wherein the packet further comprises an address field corresponding to the other device.

4. The apparatus of claim 1 , wherein the other device comprises a memory device.

5. The apparatus of claim 1 , wherein the wake message is to activate read/write activities.

6. The apparatus of claim 1 , wherein the interconnect comprises a point-to-point interconnect.

7. The apparatus of claim 1 , wherein the interconnect utilizes a specification-defined protocol.

8. The apparatus of claim 1 , wherein the wake message is sent to propagate the message downstream from the apparatus to the other device.

9. The apparatus of claim 1 , wherein the resource comprises a hardware component.

10. A method comprising:
generating a wake message, wherein the wake message comprises a packet to include at least twelve bytes, the packet includes at least one code field to include a particular code defined to indicate that the packet comprises a wake message, and the particular code comprises at least five bits, wherein the packet further comprises an address field, a tag field, a field to identify length of the packet, and an identifier field to identify the source of the packet; and
sending the wake message to another device over an interconnect, wherein the wake message is to cause a resource of the other device to be activated.

11. The method of claim 10 , wherein the wake message comprises an in-band wake message.

12. The method of claim 10 , wherein the packet further comprises an address field corresponding to the other device.

13. The method of claim 10 , wherein the wake message is to activate read/write activities.

14. The method of claim 10 , wherein the interconnect comprises a point-to-point interconnect.

15. The method of claim 10 , wherein the resource comprises a hardware resource.

16. An apparatus comprising:
a processor;
a receiver to receive a wake message from another device over an interconnect, wherein the wake message comprises a packet to include at least twelve bytes, the packet includes at least one code field to include a particular code to indicate that the packet comprises a wake message, and the particular code comprises at least five bits, wherein the packet further comprises an address field, a tag field, a field to identify length of the packet, and an identifier field to identify the source of the packet; and
a resource manager comprising circuitry to cause a resource to be activated.

17. The apparatus of claim 16 , wherein the wake message comprises an in-band wake message.

18. The apparatus of claim 16 , wherein the packet further comprises an address field corresponding to the other device.

19. The apparatus of claim 16 , wherein the wake message is to activate read/write activities.

20. The apparatus of claim 16 , wherein the interconnect comprises a point-to-point interconnect.

21. The apparatus of claim 16 , wherein the resource comprises a hardware resource.

22. A system comprising:
a first device; and
a second device connected to the first device by an interconnect, wherein the second device comprises:
a processor;
protocol logic implemented in hardware to generate a wake message, wherein the wake message comprises a packet to include at least twelve bytes, the packet includes at least one code field to include a particular code defined to indicate that the packet comprises a wake message, and the particular code comprises at least five bits, wherein the packet further comprises an address field, a tag field, a field to identify length of the packet, and an identifier field to identify the source of the packet; and
a transmitter to send the wake message to the first device over the interconnect, wherein the wake message is to cause a resource of the other device to be activated.

23. The system of claim 22 , wherein the first device comprises a memory device.

24. The system of claim 22 , wherein the wake message comprises an in-band wake message.

25. The system of claim 22 , wherein the packet further comprises an address field corresponding to the other device.

26. The system of claim 22 , wherein the wake message is to activate read/write activities.

27. The system of claim 22 , wherein the interconnect comprises a point-to-point interconnect.

28. A system comprising:
means for generating a wake message, wherein the wake message comprises a packet to include at least twelve bytes, the packet includes at least one code field to include a particular code to indicate that the packet comprises a wake message, and the particular code comprises at least five bits, wherein the packet further comprises an address field, a tag field, a field to identify length of the packet, and an identifier field to identify the source of the packet; and
means for sending the wake message to another device over an interconnect, wherein the wake message is to cause a resource of the other device to be activated.

Assignees

• Intel Corp

Inventors

• Kwa Seh W
• Songer Neil W
• Gough Rob
• Harriman David J

Classifications

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• Y02D10/151

  Cross-Sectional Technologies · mapped topic

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• G06F1/3209 Primary

  Monitoring remote activity, e.g. over telephone lines or network connections · CPC title

• G06F13/4265

  on a point to point bus (G06F13/4247, G06F13/4282 take precedence) · CPC title