Solid state memory thermal regulation

Patent metadata

Field	Value
Publication number	US-10146279-B2
Application number	US-201615087548-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Feb 22, 2013
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature. The temperature regulating system tightly regulates the temperature of solid state memory chips to within a nominal operating temperature range selected to extend the lifetime and/or improve the endurance and reliability of the solid state memory. The temperature regulating system may regulate different memory chips to different nominal temperatures based on the operations being performed and lifetime factors for the memory chips including current health and prior use.

First claim

The invention claimed is:

1. A storage system comprising:
a memory chamber comprising a plurality of memory devices configured to store data;
a plurality of temperature sensors thermally coupled to the plurality of memory devices;
a first cooling system configured to remove heat from the memory chamber;
a heating system comprising a plurality of heating elements; and
a temperature regulating system configured to cause the first cooling system to remove heat from the memory chamber, to cause a first one of the plurality of heating elements to provide a first amount of heat to a first subset of the plurality of memory devices, and to cause a second one of the plurality of heating elements to provide a second amount of heat to a second subset of the plurality of memory devices, thereby maintaining a temperature of the plurality of memory devices within a first predetermined range,
wherein the first cooling system is configured to remove heat from the first subset of the plurality of memory devices at the same time as the first one of the plurality of heating elements providing the first amount of heat to the first subset of the plurality of memory devices.

2. The storage system of claim 1 , wherein the plurality of memory devices is disposed on a plurality of memory blades arranged as an array in the memory chamber.

3. The storage system of claim 2 , wherein the temperature regulating system is configured to cause the first cooling system to remove more heat from a middle of the array than an edge of the array.

4. The storage system of claim 2 , wherein one of the plurality of memory blades comprises a heat spreader coupled to a third subset of plurality of memory devices and a third one of the plurality of heating elements, and wherein the third one of the plurality of heating elements is configured to provide heat to the third subset of plurality of memory devices through the heat spreader.

5. The storage system of claim 2 , wherein one of the plurality of memory blades comprises a thermal layer coupled to a third subset of plurality of memory devices and a third one of the plurality of heating elements, and wherein the third one of the plurality of heating elements is configured to provide heat to the third subset of plurality of memory devices through the thermal layer.

6. The storage system of claim 1 , wherein the first cooling system comprises a plurality of cooling elements, and wherein the temperature regulating system is configured to estimate a lifetime of a first one of the plurality of cooling elements based on a performance disparity between the first one of the plurality of cooling elements and a second one of the plurality of cooling elements.

7. The storage system of claim 1 , further comprising a digital chamber including electronic components, wherein the digital chamber is coupled to a second cooling system configured to remove heat from the digital chamber, and the temperature regulating system is configured to regulate a temperature of the components within a second predetermined range.

8. The storage system of claim 1 , wherein the temperature regulating system is configured to determine the first predetermined range based in part on an operating condition of the plurality of memory devices.

9. The storage system of claim 1 , wherein the temperature regulating system is configured to modify an activity level of the first subset of the plurality of memory devices to regulate a temperature of the first subset of the plurality of memory devices.

10. The storage system of claim 1 , wherein the first subset of the plurality of memory devices comprises a single memory device.

11. The storage system of claim 1 , wherein the temperature regulating system is configured to cause the first one and the second one of the plurality of heating elements to provide the first amount of heat and the second amount of heat, respectively, based, at least in part, on information from at least one of the plurality of temperature sensors.

12. A method of regulating temperature in a storage system, the method comprising:
removing heat, by a first cooling system, from a memory chamber comprising a plurality of memory devices configured to store data;
providing, by a first heating element in a heating system, a first amount of heat to a first subset of the plurality of memory devices, at the same time as removing heat, by the first cooling system, from the first subset of the plurality of memory devices;
providing, by a second heating element in the heating system, a second amount of heat to a second subset of the plurality of memory devices, thereby maintaining a temperature of the plurality of memory devices within a first predetermined range.

13. The method of claim 12 , wherein providing the first amount of heat and the second amount of heat comprises providing the first amount of heat and the second amount of heat based, at least in part, on information from a temperature sensor.

14. The method of claim 12 , wherein the plurality of memory devices is disposed on a plurality of memory blades arranged as an array in the memory chamber, and the method further comprises removing more heat from a middle of the array than an edge of the array.

15. The method of claim 14 , wherein one of the plurality of memory blades comprises a heat spreader coupled to a third subset of plurality of memory devices and a third one of the plurality of heating elements, and the method comprises providing heat, by the third one of the plurality of heating elements, to the third subset of plurality of memory devices through the heat spreader.

16. The method of claim 14 , wherein one of the plurality of memory blades comprises a thermal layer coupled to a third subset of plurality of memory devices and a third one of the plurality of heating elements, and the method comprises providing heat, by the third one of the plurality of heating elements, to the third subset of plurality of memory devices through the thermal layer.

17. The method of claim 12 , further comprising determining the first predetermined range based in part on an operating condition of the plurality of memory devices.

18. The method of claim 12 , further comprising modifying an activity level of the first subset of the plurality of memory devices to regulate a temperature of the first subset of the plurality of memory devices.

19. The method of claim 12 , wherein the first subset of the plurality of memory devices comprises a single memory device.

20. The method of claim 12 , further comprising regulating a temperature of components within a digital chamber to a second predetermined range by causing a second cooling system coupled to the digital chamber to remove heat from the digital chamber.

Assignees

• Skyera Llc
• Western Digital Tech Inc

Inventors

• Vyshetsky Dmitry

Classifications

• G05B15/02

  electric · CPC title

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F1/20

  Cooling means · CPC title