Monitor system and method for semiconductor processes

Patent metadata

Field	Value
Publication number	US-10146215-B2
Application number	US-201314091444-A
Country	US
Kind code	B2
Filing date	Nov 27, 2013
Priority date	Nov 27, 2013
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A method for monitoring a process in a semiconductor processing facility and a monitor system are provided. A plurality of wafers are processed according to a process. Data on the processing is collected, and the collecting includes, for each wafer of the plurality of wafers, determining that a processing event has occurred, and recording a time associated with the processing event. An amount of time between the recorded times is calculated for consecutively processed wafers. A set of control limits for the process is determined based on the calculated amounts of time. The set of control limits define a range of acceptable values for the amount of time. Second wafers are processed according to the process. A problem in the processing of the second wafers is identified based on the set of control limits. The problem is identified as the second wafers are being processed.

First claim

It is claimed:

1. A method for monitoring a process in a semiconductor processing facility, the method comprising:
processing a first set of wafers according to a multiple-step process and collecting data during the processing of the first set of wafers, wherein the data comprises a time for each of the wafers for each step of the multiple-step process;
dynamically tuning a set of control limits for the multiple-step process during the processing of the wafers in an automatic manner, wherein each control limit in the set of control limits is associated with a particular wafer, wherein each control limit in the set of control limits is based on times associated with previously processed wafers in the first set of wafers, and wherein the tuning of each control limit in the set of control limits comprises modifying that control limit multiple times during the processing of the first set of wafers, that control limit being modified on a real-time basis based on the times associated with the previously processed wafers;
identifying a problem in the processing of the wafers based on the set of control limits and by analyzing the data at a macro level of granularity that is indicative of an amount of time required to complete all steps of the multiple-step process;
after the identifying of the problem, identifying a bottleneck step of the multiple-step process by analyzing the data at a micro level of granularity that is indicative of an amount of time required to complete a single step of the multiple-step process, wherein the problem is identified as the first set of wafers are being processed,
wherein the multiple-step process is adjusted based on the identified bottleneck step, and
wherein a second set of wafers are processed based on the adjusted multiple-step process.

2. The method of claim 1 , further comprising:
collecting the data during the processing of the first set of wafers, wherein the data is collected on a real time basis, and wherein the problem is identified by comparing the data to the set of control limits or by comparing data derived from the collected data to the set of control limits.

3. The method of claim 2 , wherein the derived data is a calculated amount of time associated with consecutively processed wafers of the first set of wafers, and wherein the problem indicates that the calculated amount of time is outside of the range of acceptable values for the amount of time.

4. The method of claim 1 , further comprising:
processing a single wafer of the first set of wafers according to the process, wherein the processing of the single wafer includes a plurality of steps, wherein the bottleneck step is a particular step of the plurality of steps, and wherein the bottleneck step limits a throughput of the process more than all other steps of the plurality of steps.

5. The method of claim 4 , wherein the micro level analysis is performed at a higher granularity as compared to the macro level analysis.

6. The method of claim 1 , wherein the process includes a plurality of steps, and wherein the set of control limits includes, for each step of the plurality of steps, i) an upper control limit for the amount of time, and ii) a lower control limit for the amount of time.

7. The method of claim 1 , wherein each step of the plurality of steps corresponds to a different process recipe.

8. The method of claim 1 , further comprising:
collecting the data during the processing of the first set of wafers, wherein the collecting includes, for each wafer of the first set of wafers:
determining that a processing event has occurred, and
recording a time associated with the processing event; and

modifying the set of control limits based on the recorded times for the first set of wafers.

9. The method of claim 1 , further comprising:
outputting an alert signal, wherein the alert signal indicates that the problem has been identified, and wherein the alert signal is output contemporaneously with an occurrence of the problem.

10. The method of claim 1 , wherein the problem is indicative of a low throughput for the process.

11. The method of claim 1 , the method further comprising:
collecting the data during the processing of the first set of wafers, wherein the data is collected on a real time basis, and wherein the collecting includes, for each wafer:
determining a start of a processing event and a stop of a processing event for that wafer; and
recording times associated with the start of the processing event and the stop of the processing event;

calculating, for each wafer, a time interval between each wafer and a previous wafer based on the recorded times;
modifying, for each wafer, the set of control limits based on calculated time intervals for previously processed wafers, wherein the set of control limits includes, for each step of the plurality of steps, i) an upper control limit and ii) a lower control limit;
comparing, prior to the identifying, the calculated time interval for each wafer to the modified set of control limits for that wafer; and
outputting an alert signal, wherein the alert signal indicates that the calculated time interval (i) exceeds the upper control limit or (ii) falls short of the lower control limit.

12. A monitor system for a semiconductor processing facility, the monitor system comprising:
semiconductor processing equipment configured to process a first plurality of wafers according to a multiple-step process;
a controller configured to collect data during the processing of the first plurality of wafers, wherein the data comprises a time for each of the wafers in the plurality of wafers for each step of the multiple-step process;
an event database configured to store the collected data; and
a statistical process control (SPC) system configured to
identify a problem in the processing of the first plurality of wafers according to the multiple-step process based on a set of control limits and by analyzing the data collected during the processing of the first plurality of wafers at a macro level of granularity that is indicative of an amount of time required to complete all steps of the multiple-step process,
dynamically tune the set of control limits during the processing of the first plurality of wafers in an automatic manner, wherein each control limit in the set of control limits is associated with a particular wafer, wherein each control limit in the set of control limits is based on times associated with previously processed wafers in the first plurality of wafers, and wherein the tuning of each control limit in the set of control limits comprises modifying that control limit multiple times during the processing of the first plurality of wafers, that control limit being modified on a real-time basis based on the times associated with the previously processed wafers, and
after the identifying of the problem, identify a bottleneck step of the multiple-step process by analyzing the data at a micro level of granularity that is indicative of an amount of time required to complete a single step of the multiple-step process, wherein the problem is identified in a real time manner as the first plurality of wafers are being processed,

wherein the multiple-step process is adjusted based on the identified bottleneck step, and
wherein a second plurality of wafers are processed based on the adjusted multiple-step process.

13. The monitor system of claim 12 , wherein the data is collected during the processing of the first plurality of wafers in the real time manner, and wherein the problem is identified by comparing the data to the set of control limits or by comparing data derived from the collected data t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Chih-Wei
• Lee Feng-Ning

Classifications

• G05B19/418 Primary

  Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] · CPC title

• Y02P90/02

  Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] · CPC title

• G05B2219/42001

  Statistical process control spc · CPC title

• G05B23/024

  Quantitative history assessment, e.g. mathematical relationships between available data; Functions therefor; Principal component analysis [PCA]; Partial least square [PLS]; Statistical classifiers, e.g. Bayesian networks, linear regression or correlation analysis; Neural networks · CPC title

• G05B2219/45031

  Manufacturing semiconductor wafers · CPC title