Parallax barrier and fabricating method thereof, display panel and display device

Patent metadata

Field	Value
Publication number	US-10146059-B2
Application number	US-201414436763-A
Country	US
Kind code	B2
Filing date	Sep 23, 2014
Priority date	May 4, 2014
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

The embodiments of the present invention disclose a parallax bather and a fabricating method thereof. The parallax barrier comprises a first transparent conducting layer (35), a second transparent conducting layer (36), and an insulating layer (37) between the first transparent conducting layer (35) and the second transparent conducting layer (36). The first transparent conductive layer (35) is formed into a plurality of signal electrode lines (350), and the second transparent conductive layer (36) is formed into a plurality of common electrode lines (360). The signal electrode lines (350) and the common electrode lines (360) are arranged alternately, and the common electrode lines (360) are located in a gap between adjacent signal electrode lines (350) with the insulating layer (37) in between.

First claim

What is claimed is:

1. A parallax barrier comprising:
a first transparent conducting layer, a second transparent conducting layer, and an insulating layer between the first transparent conducting layer and the second transparent conducting layer;
the first transparent conductive layer being formed into a plurality of signal electrode lines, and the second transparent conductive layer being formed into a plurality of common electrode lines, the signal electrode lines and the common electrode lines are arranged alternately, and the common electrode lines are located in a gap between adjacent signal electrode lines, with the insulating layer in between,
a first transparent substrate and a second transparent substrate cell assembled, and a transparent liquid filled between the first transparent substrate and the second transparent substrate; the signal electrode lines and the common electrode lines being disposed on the first transparent substrate, and a continuous common electrode layer being disposed on the second transparent substrate, a signal lead line and a common lead line arranged on edges of the parallax barrier;
wherein the signal lead line and the common lead line are disposed in a same metal layer; the signal lead line is electrically connected with the signal electrode lines, and the common electrode lines and the common electrode layer on the second transparent substrate are electrically connected by the common lead line to receive a same voltage signal;
the signal lead line is electrically connected with the signal electrode lines through direct contact by overlapping without via holes, and the common lead line is electrically connected with the common electrode lines through via holes passing through the insulating layer; or, the common lead line is electrically connected with the common electrode lines through direct contact by overlapping without via holes, and the signal lead line is electrically connected with the signal electrode lines through via holes passing through the insulating layer.

2. The parallax barrier according to claim 1 , wherein the metal layer is located above or below the first transparent conducting layer; or the metal layer disposed above or below the second transparent conducting layer.

3. The parallax barrier according to claim 2 , wherein in a case where the metal layer is disposed above or below the first transparent conducting layer, the signal lead line is electrically connected to the signal electrode lines by direct contact without via holes, and the common lead line is electrically connected to the common electrode lines by the via holes passing through the insulating layer;
in a case where the metal layer is disposed above or below the second transparent conducting layer, the signal lead line is electrically connected with the signal electrode lines by the via holes passing through the insulating layer, and the common lead line is electrically connected to the common electrode lines by direct contact without via holes.

4. A display device comprising the parallax barrier according to claim 1 .

5. The display device according to claim 4 , wherein the metal layer is located above or below the first transparent conducting layer; or the metal layer disposed above or below the second transparent conducting layer.

6. The display device according to claim 5 , wherein in a case where the metal layer is disposed above or below the first transparent conducting layer, the signal lead line is electrically connected to the signal electrode lines by direct contact without via holes, and the common lead line is electrically connected with the common electrode lines by the via holes passing through the insulating layer; in a case where the metal layer is disposed above or below the second transparent conducting layer, the signal lead line is electrically connected to the signal electrode lines by the via holes passing through the insulating layer, and the common lead line is electrically connected to the common electrode lines by direct contact without via holes.

7. The display device as in claim 4 , wherein the transparent liquid comprises a transparent electrolyte solution.

8. The display device as in claim 7 , wherein the transparent electrolyte solution comprises at least two parts, a reversible reactant and an electrolyte solution.

9. The parallax barrier as in claim 1 wherein the transparent liquid comprises a transparent electrolyte solution.

10. The parallax barrier as in claim 9 , wherein the transparent electrolyte solution comprises at least two parts a reversible reactant and an electrolyte solution.

11. A method of fabricating a parallax barrier comprising steps of forming a first cell assembling substrate and a second cell assembling substrate; and cell assembling the first cell assembling substrate and the second cell assembling substrate, and injecting liquid crystal between the first cell assembling substrate and the second cell assembling substrate, wherein the step of forming the first cell assembling substrate comprises:
forming a first transparent conductive film layer over a first substrate, and forming a plurality of common electrode lines spaced apart by patterning process;
forming an insulating layer over the first transparent conductive film layer and via holes passing through the insulating layer;
forming a second transparent conductive film layer over the insulating layer, and forming a plurality of signal electrode lines spaced apart by a patterning process, and the common electrode lines are located in a gap between adjacent signal electrode lines with the insulating layer in between;
wherein the step of forming the second cell assembling substrate comprises forming a continuous common electrode layer over a second substrate;
wherein the step of forming the first cell assembling substrate further comprises:
forming a metal layer over a first substrate, and forming a signal lead line and a common lead line by a patterning process to the metal layer, the signal lead line configured to be electrically connected to the signal electrode lines through direct contact by overlapping without via holes and the common lead lines configured to electrically connect with the common electrode lines through the via holes passing through the insulating layer, or the common lead line configured to be electrically connected with the common electrode lines through direct contact by overlapping without via holes and the signal lead line configured to be electrically connected to the signal electrode lines through the via holes passing through the insulating layer;
the step of forming the metal layer is performed before or after the step of forming the common electrode lines, or the step of forming the metal layer is performed before or after the step of forming the signal electrode lines.

12. The method according to claim 11 , wherein in a case that the step of forming the metal layer is performed before or after the step of forming the common electrode lines,
the signal lead lines are electrically connected to the signal electrode lines by the via holes passing through the insulating layer, and the common lead lines are electrically connected to the common electrode lines by direct contact by overlapping without via holes.

13. The method according to claim 11 , wherein in a case that the step of forming the metal layer is performed before or after the step of forming the signal electrode lines,
the signal lead lines are electrically connected to the signal electrode lines by direct contact by overlapping without via holes, and the common lead line is electrically connected to the common electrode lines through the v

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Guo Huibin
• Zhang Zhenyu
• Wang Shoukun
• Li Liangliang
• Feng Yuchun

Classifications

• H04N13/229

  using lenticular lenses, e.g. arrangements of cylindrical lenses · CPC title

• G02B30/27 Primary

  involving lenticular arrays · CPC title

• G02F1/1345

  Conductors connecting electrodes to cell terminals · CPC title

• G02F1/1341

  Filling or closing of cells · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title