Front-end and back-end processing circuits and POC circuit

Patent metadata

Field	Value
Publication number	US-10142586-B2
Application number	US-201515536955-A
Country	US
Kind code	B2
Filing date	Jun 17, 2015
Priority date	Feb 9, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

The disclosure discloses a back-end circuit for processing an analog video signal and direct current power, a front-end circuit for processing an analog video signal and direct current power and a Power Over Coaxia (POC) circuit for an analog video signal. Each of the back-end processing circuit and the front-end processing circuit includes an analog video signal passing circuit configured to block the direct current power and let the analog video signal pass and a direct current power passing circuit configured to block the analog video signal and let the direct current power pass, so that the analog video signal may be isolated from the direct current power and the analog video signal may be superimposed to the direct current power without mutual influence and exclusion to realize a function of superimposing the direct current power on an analog high-definition video cable.

First claim

The invention claimed is:

1. A back-end circuit for processing an analogue video signal and direct current power, comprising:
an analogue video signal passing circuit configured to block the direct current power and let the analogue video signal pass; and
a direct current power passing circuit configured to block the analogue video signal and let the direct current power pass,
wherein the analogue video signal passing circuit comprises a capacitor C 2 , the direct current power passing circuit comprises a diode D 2 and an inductor L 2 , one end of the capacitor C 2 is connected with a video signal end, the other end of the capacitor C 2 is connected with one end of the inductor L 2 and an anode of the diode D 2 respectively, and both the other end of the inductor L 2 and a cathode of the diode D 2 are connected with a power input end,
wherein the back-end circuit further comprises a superimposed circuit, connected between the direct current power passing circuit and the direct current power, and configured to implement high impedance to the analogue video signal, wherein the superimposed circuit comprises a capacitor, a triode and a resistor, and when the triode is in an amplification state, high impedance to the analogue video signal is implemented by utilizing a characteristic that the capacitor presents low impedance to an alternating current signal and adopting resistors with different resistances.

2. The processing circuit as claimed in claim 1 , wherein the anode of the diode D 2 is further connected with a matching circuit, the matching circuit is a termination matching circuit, and the termination matching circuit comprises a Thevenin termination matching circuit and an RC termination matching circuit.

3. The processing circuit as claimed in claim 1 , wherein the video signal end is further connected with a video processing circuit, the video processing circuit comprises a video Analogue/Digital (A/D) conversion circuit and a low-pass filter, one end of the low-pass filter is connected with the video A/D conversion circuit, and the other end of the low-pass filter is connected with one end of the capacitor C 2 .

4. The processing circuit as claimed in claim 1 , wherein the cathode of the diode D 2 is further connected with a superimposed circuit configured to implement high impedance to the analogue video signal, the superimposed circuit comprises a capacitor, a triode and a resistor, and when the triode is in an amplification state, high impedance to the analogue video signal is implemented by utilizing a characteristic that the capacitor presents low impedance to an alternating current signal and adopting resistors with different resistances.

5. The processing circuit as claimed in claim 4 , wherein the superimposed circuit comprises a resistor R 4 , a capacitor C 1 , a triode Q 3 , a resistor R 5 , a triode Q 4 and a resistor R 6 , one end of the resistor R 4 is connected with a power input end, a collector of the triode Q 3 and a collector of the triode Q 4 respectively, the other end of the resistor R 4 is connected with one end of the capacitor C 1 and a base of the triode Q 3 respectively, an emitter of the triode Q 3 is connected with one end of the resistor R 5 and a base of the triode Q 4 respectively, an emitter of the triode Q 4 is connected with one end of the resistor R 6 , and the other end of the capacitor C 1 is connected with the other end of the resistor R 5 , the other end of the resistor R 6 and the cathode of the diode D 2 respectively.

6. The processing circuit as claimed in claim 4 , wherein the superimposed circuit comprises a resistor R 4 , a capacitor C 1 , a triode Q 3 , a resistor R 5 , a triode Q 4 and a resistor R 6 , one end of the resistor R 4 is connected with a power input end, a collector of the triode Q 3 and a collector of the triode Q 4 respectively, the other end of the resistor R 4 is connected with one end of the capacitor C 1 and a base of the triode Q 3 , an emitter of the triode Q 3 is connected with one end of the resistor R 5 and a base of the triode Q 4 respectively, an emitter of the triode Q 4 is connected with one end of the resistor R 6 , the other end of the capacitor C 1 is connected with the anode of the diode D 2 and the other end of the resistor R 5 respectively, and the other end of the resistor R 6 is connected with the cathode of the diode D 2 .

7. The processing circuit as claimed in claim 4 , wherein the superimposed circuit comprises a resistor R 4 , a capacitor C 1 , a triode Q 3 , a resistor R 5 , a triode Q 4 and a resistor R 6 , one end of the resistor R 4 is connected with a power input end, a collector of the triode Q 3 and a collector of the triode Q 4 respectively, the other end of the resistor R 4 is connected with one end of the capacitor C 1 and a base of the triode Q 3 respectively, an emitter of the triode Q 3 is connected with one end of the resistor R 5 and a base of the triode Q 4 respectively, an emitter of the triode Q 4 is connected with one end of the resistor R 6 , the other end of the capacitor C 1 is connected with the anode of the diode D 2 , and the other end of the resistor R 5 is connected with the other end of the resistor R 6 and the cathode of the diode D 2 respectively.

8. The processing circuit as claimed in claim 4 , wherein the superimposed circuit comprises a capacitor C 21 , a resistor R 21 , a resistor R 23 , a resistor R 24 , a triode Q 21 , a triode Q 22 and a resistor R 22 , one end of the capacitor C 21 is connected with a power input end, one end of the resistor R 21 , one end of the resistor R 23 and one end of the resistor R 24 respectively, the other end of the capacitor R 21 is connected with the other end of the resistor R 21 , a base of the triode Q 21 and one end of the resistor R 22 respectively, an emitter of the triode Q 21 is connected with the other end of the resistor R 23 and a base of the triode Q 22 respectively, an emitter of the triode Q 22 is connected with the other end of the resistor R 24 , and the other end of the resistor R 22 is connected with a collector of the triode Q 21 , a collector of the triode Q 22 and the cathode of the diode D 2 respectively.

9. The processing circuit as claimed in claim 1 , wherein the cathode of the diode D 2 is further connected with an over-current protection circuit, the over-current protection circuit comprises a resistor R 1 , a triode Q 1 , a triode Q 2 , a resistor R 2 , an adjustable precision voltage regulator D 1 and a resistor R 3 , one end of the resistor R 1 is connected with a power input end, a collector of the triode Q 1 and a collector of the triode Q 2 respectively, an emitter of the triode Q 1 is connected with a base of the triode Q 2 and one end of the resistor R 2 respectively, an emitter of the triode Q 2 is connected with the other end of the resistor R 2 , a regulation end of the adjustable precision voltage regulator D 1 and one end of the resistor R 3 respectively, the other end of the resistor R 1 is connected with a base of the triode Q 1 and an input end of the adjustable precision voltage regulator D 1 respectively, and an output end of the adjustable precision voltage regulator D 1 is connected with the other end of the resistor R 3 and the cathode of the diode D 2 respectively.

10. The processing circuit as claimed in claim 4 , wherein one end of the superimposed circuit is connected with the cathode of the diode D 2 , the other end of the superimposed circuit is connected with an over-current protection circuit, the over-current protection circuit comprises a resistor R 1 , a triode Q 1 , a triode Q 2 , a resistor R 2 , an adjustable precision voltage regulator

Assignees

• Hangzhou Hikvision Digital Tec
• Hangzhou Hikvision Digital Tec

Inventors

• Ye Min
• Zhang Liang
• Luo Mingling

Classifications

• H04B2203/5487

  cables · CPC title

• H04N5/14

  Picture signal circuitry for video frequency region (cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00) · CPC title

• H04N7/10

  Adaptations for transmission by electrical cable (H04N7/12 takes precedence) · CPC title

• H04B3/548 Primary

  the power on the line being DC (arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02) · CPC title

• H04N7/102 Primary

  Circuits therefor, e.g. noise reducers, equalisers, amplifiers (H04N7/108 takes precedence) · CPC title