Source follower

US10141897B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10141897-B2
Application numberUS-201715831220-A
CountryUS
Kind codeB2
Filing dateDec 4, 2017
Priority dateDec 7, 2016
Publication dateNov 27, 2018
Grant dateNov 27, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A source follower includes a first transistor, a first output module, a second transistor, a second output module and a feedback module. The first terminal and the control terminal of the first transistor are configured to respectively receive a first base voltage and a first control voltage. The second terminal of the first transistor and the first output module are electrically connected to a first output terminal. The first terminal and the control terminal of the second transistor are configured to respectively receive a first base voltage and a second control voltage. The second terminal of the second transistor and the second output module are electrically connected to a second output terminal. The feedback module is electrically connected to the control terminal of the first transistor, the control terminal of the second transistor and a reference node of the second output module.

First claim

Opening claim text (preview).

What is claimed is: 1. A source follower, comprising: a first transistor having a first terminal, a second terminal and a control terminal, with the first terminal of the first transistor configured to receive a first base voltage, the second terminal of the first transistor electrically connected to a first output terminal, the control terminal of the first transistor configured to receive a first control voltage, and the first transistor configured to generate a first current according to the first control voltage; a first output module electrically connected to the first output terminal and providing an output voltage to the first output terminal according to an input voltage signal and the first current; a second transistor having a first terminal, a second terminal and a control terminal, with the first terminal of the second transistor configured to receive the first base voltage, the second terminal of the second transistor electrically connected to a second output terminal, the control terminal of the second transistor configured to receive the first control voltage and the second transistor configured to generate a second current according to the first control voltage; a second output module electrically connected to the second output terminal and providing a common-mode voltage to the second output terminal according to a second base voltage and the second current; and a feedback module electrically connected to the control terminal of the first transistor, the control terminal of the second transistor and a reference node in the second output module, the feedback module configured to regulate a voltage level of the reference node and a voltage level of the first control voltage according to a reference voltage, wherein the feedback module comprising: an amplifier, with a first input terminal of the amplifier configured to receive the reference voltage, a second input terminal of the amplifier electrically connected to the reference node, an output terminal of the amplifier electrically connected to the control terminal of the first transistor and the control terminal of the second transistor, and the amplifier providing the first control voltage through the output terminal. 2. The source follower according to claim 1 , wherein the first output module has another reference node, the feedback module is electrically connected to said another reference node, the feedback module regulates a voltage level of said another reference node according to the reference voltage, and the feedback module further comprises: a first differential pair having a first control terminal, a second control terminal, a first current terminal, a second current terminal and a third current terminal, with the first control terminal electrically connected to the reference node, the second control terminal configured to receive the reference voltage, the first differential pair configured to control current flowing through the first current terminal, the second current terminal and the third current terminal according to a voltage level of the first control terminal and a voltage level of the second control terminal; a second differential pair having a third control terminal, a fourth control terminal, a fourth current terminal, a fifth current terminal and a sixth current terminal, with the third control terminal configured to receive the reference voltage, the fourth control terminal electrically connected to said another reference node, and the second differential pair configured to control current flowing through the fourth current terminal, the fifth current terminal and the sixth current terminal according to a voltage level of the third control terminal and a voltage level of the fourth control terminal; and a bus unit electrically connected to the first transistor and the second transistor and having a first bus terminal and a second bus terminal, with the first bus terminal electrically connected to the third current terminal and the fifth current terminal, the second bus terminal electrically connected to the second current terminal and the sixth current terminal, the bus unit configured to control current flowing through the first transistor and current flowing though the second transistor according to current flowing through the third current terminal, current flowing through the fourth current terminal, current flowing through the fifth current terminal and current flowing through the sixth current terminal. 3. The source follower according to claim 2 , wherein the first differential pair comprises a fifth transistor and a sixth transistor, the second differential pair comprises a seventh transistor and a eighth transistor, a first terminal of the fifth transistor is electrically connected to the first current terminal, a second terminal of the fifth transistor is electrically connected to the second current terminal, a control terminal of the fifth transistor is electrically connected to the first control terminal, a first terminal of the sixth transistor is electrically connected to the first current terminal, a second terminal of the sixth transistor is electrically connected to the third current terminal, a control terminal of the sixth transistor is electrically connected to the second control terminal, a first terminal of the seventh transistor is electrically connected to the fourth current terminal, a second terminal of the seventh transistor is electrically connected to the fifth current terminal, a control terminal of the seventh transistor is electrically connected to the third control terminal, a first terminal of the eighth transistor is electrically connected to the fourth current terminal, a second terminal of the eighth transistor is electrically connected to the sixth current terminal, a control terminal of the eighth transistor is electrically connected to the fourth control terminal. 4. The source follower according to claim 2 , wherein the bus unit comprises a ninth transistor and a tenth transistor, a first terminal of the ninth transistor is electrically connected to the bus unit, a second terminal of the ninth transistor is configured to receive the second base voltage, a control terminal of the ninth transistor is electrically connected to the first bus terminal, a first terminal of the tenth transistor is electrically connected to the second bus terminal, a second terminal of the tenth transistor is configured to receive the second base voltage, and a control terminal of the tenth transistor is electrically connected to the second bus terminal. 5. The source follower according to claim 4 , further comprising a eleventh transistor and a twelfth transistor, with a second terminal of the eleventh transistor configured to receive the second base voltage, a control terminal of the eleventh transistor is electrically connected to the control terminal of the tenth transistor, a first terminal of the twelfth transistor is configured to receive the first base voltage, a second terminal of the twelfth transistor is electrically connected to a first terminal of the eleventh transistor, a control terminal of the twelfth transistor is electrically connected to the second terminal of the twelfth transistor, and the control terminal of the twelfth transistor is electrically connected to the control terminal of the first transistor and the control terminal of the second transistor. 6. The source follower according to claim 5 , further comprising a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a current source, with a first terminal of the thirteenth transistor configured to receive the first base voltage, a second terminal of the thirteenth transistor electrically connected to the first current terminal, a first terminal of the fourteenth transistor configured to receive the first

Assignees

Inventors

Classifications

  • in field-effect transistor amplifiers · CPC title

  • with field-effect devices (H03F3/347 takes precedence) · CPC title

  • the source follower has a controlled source circuit, the controlling signal being derived from the drain circuit of the follower · CPC title

  • with field-effect devices · CPC title

  • there being a feedback over one or more internal stages in the global amplifier · CPC title

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What does patent US10141897B2 cover?
A source follower includes a first transistor, a first output module, a second transistor, a second output module and a feedback module. The first terminal and the control terminal of the first transistor are configured to respectively receive a first base voltage and a first control voltage. The second terminal of the first transistor and the first output module are electrically connected to a…
Who is the assignee on this patent?
Silicon Integrated Systems Corp, Silicon Intergrated Systems Corp
What technology area does this patent fall under?
Primary CPC classification H03F1/342. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).