Solar cells having differentiated P-type and N-type architectures

Patent metadata

Field	Value
Publication number	US-10141462-B2
Application number	US-201615384061-A
Country	US
Kind code	B2
Filing date	Dec 19, 2016
Priority date	Dec 19, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.

First claim

What is claimed is:

1. A solar cell, comprising:
an N-type semiconductor substrate having a light-receiving surface and a back surface;
a plurality of N-type polycrystalline silicon regions disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate; and
a plurality of P-type polycrystalline silicon regions disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate, wherein a total area of the plurality of N-type polycrystalline silicon regions is greater than a total area of the plurality of P-type polycrystalline silicon regions in the plurality of corresponding trenches.

2. The solar cell of claim 1 , wherein the total area of the plurality of N-type polycrystalline silicon regions is greater than the total area of the plurality of P-type polycrystalline silicon regions in the plurality of corresponding trenches by a ratio of 15:1 or more.

3. The solar cell of claim 1 , wherein the plurality of P-type polycrystalline silicon regions overlap a portion of the plurality of N-type polycrystalline silicon regions.

4. The solar cell of claim 1 , wherein each of the plurality of N-type polycrystalline silicon regions has a width greater than a width of each of the plurality of P-type polycrystalline silicon regions by a ratio of 5:1 or more.

5. The solar cell of claim 1 , wherein each of the plurality of N-type polycrystalline silicon regions has a thickness relative to a thickness of each of the plurality of P-type polycrystalline silicon regions by a ratio of 3:1 or less.

6. The solar cell of claim 1 , wherein each of the plurality of trenches has a depth approximately in the range of 0.1-3 microns from the back surface and into the N-type semiconductor substrate.

7. The solar cell of claim 1 , wherein each of the plurality of trenches has a texturized surface.

8. The solar cell of claim 1 , further comprising:
a third thin dielectric layer disposed laterally directly between adjacent ones of the N-type polycrystalline silicon regions and the P-type polycrystalline silicon regions.

9. The solar cell of claim 1 , further comprising:
a plurality of conductive contact structures electrically connected to the N-type polycrystalline silicon regions and the P-type polycrystalline silicon regions.

Assignees

• Sunpower Corp

Inventors

• Smith David D
• Waldhauer Ann
• Balu Venkatasubramani
• Tracy Kieran Mark

Classifications

• H01L31/068

  Electricity · mapped topic

• H01L31/03682

  Electricity · mapped topic

• H01L31/1804

  Electricity · mapped topic

• H01L31/02363 Primary

  Electricity · mapped topic

• H10F77/1642

  including only Group IV materials · CPC title