Vertical gate guard ring for single photon avalanche diode pitch minimization

Patent metadata

Field	Value
Publication number	US-10141458-B2
Application number	US-201615216049-A
Country	US
Kind code	B2
Filing date	Jul 21, 2016
Priority date	Jul 21, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A photon detection device includes a single photon avalanche diode (SPAD) including a multiplication junction defined at an interface between n doped and p doped layers of the SPAD in a first region of a semiconductor layer. A vertical gate structure surrounds the SPAD in the semiconductor layer to isolate the SPAD in the first region from a second region of the semiconductor layer on an opposite side of the vertical gate structure. The SPAD laterally extends within the first region of semiconductor layer to the vertical gate structure. An inversion layer is generated in the SPAD around a perimeter of the SPAD proximate to the vertical gate structure in response to a gate bias voltage coupled to the vertical gate structure. The inversion layer isolates the SPAD from the second region of the semiconductor layer on the opposite side of the vertical gate structure.

First claim

What is claimed is:

1. A photon detection device, comprising:
a single photon avalanche diode (SPAD) disposed in a first region of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined at an interface between an n doped layer and a p doped layer of the SPAD in the first region of the first semiconductor layer;
a vertical gate structure disposed in the first semiconductor layer proximate to the SPAD, wherein the vertical gate structure surrounds the SPAD to isolate the SPAD in the first region of the first semiconductor layer from a second region of the first semiconductor layer on an opposite side of the vertical gate structure, wherein the n doped layer and the p doped layer of the SPAD laterally extend within the first region of the first semiconductor layer to contact the vertical gate structure; and
a depletion layer generated around a perimeter of the SPAD at an interface of the vertical gate structure and the p doped layer in response to a gate bias voltage coupled to the vertical gate structure, wherein the depletion layer isolates the SPAD from the second region of the first semiconductor layer on the opposite side of the vertical gate structure.

2. The photon detection device of claim 1 , wherein the vertical gate structure comprises:
a doped polysilicon filled trench disposed in the first semiconductor layer proximate to the SPAD; and
a passivation layer lining the doped polysilicon filled trench, wherein the passivation layer is disposed between the doped polysilicon inside the trench and semiconductor material of the first semiconductor layer.

3. The photon detection device of claim 2 , wherein the gate bias voltage is a positive voltage coupled to the doped polysilicon inside the trench, wherein the semiconductor material of the first semiconductor layer outside of the SPAD is coupled to receive a negative operational bias voltage.

4. The photon detection device of claim 1 , wherein the multiplication junction is reversed biased above a breakdown voltage such that photons directed into the SPAD trigger an avalanche multiplication process in the multiplication junction.

5. The photon detection device of claim 4 , wherein the SPAD is formed in a front side of the first semiconductor layer, and wherein the SPAD is optically coupled to receive the photons through a back side of the first semiconductor layer.

6. The photon detection device of claim 5 , wherein the photons are near infrared light directed through the back side of the first semiconductor layer into the SPAD.

7. The photon detection device of claim 1 , wherein the first semiconductor layer is included in a first semiconductor device wafer, wherein the first semiconductor device wafer is stacked with a second semiconductor device wafer including support circuitry coupled to the SPAD, and wherein the first and second semiconductor device wafers are coupled together in a stacked chip system.

8. The photon detection device of claim 7 , wherein the support circuitry included in the second semiconductor device wafer includes quenching circuitry and time to digital converter (TDC) circuitry coupled to the SPAD.

9. The photon detection device of claim 7 , wherein the support circuitry included in the second semiconductor device wafer includes an application specific integrated circuit (ASIC) coupled to the SPAD.

10. The photon detection device of claim 1 , wherein the depletion layer is generated only in the p doped layer of the SPAR at the interface of the vertical gate structure and the p doped layer.

11. A photon sensing system, comprising:
a photon detection array having a plurality of photon detection devices, wherein each one of the photon detection devices includes:
a single photon avalanche diode (SPAD) disposed in a first region of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined at an interface between an n doped layer and a p doped layer of the SPAD in the first region of the first semiconductor layer;
a vertical gate structure disposed in the first semiconductor layer proximate to the SPAD, wherein the vertical gate structure surrounds the SPAD to isolate the SPAD in the first region of the first semiconductor layer from a second region of the first semiconductor layer on an opposite side of the vertical gate structure, wherein the n doped layer and the p doped layer of the SPAD laterally extend within the first region of the first semiconductor layer to contact the vertical gate structure; and
a depletion layer generated around a perimeter of the SPAD at an interface of the vertical gate structure and the p doped layer in response to a gate bias voltage coupled to the vertical gate structure, wherein the depletion layer isolates the SPAD from the second region of the first semiconductor layer on the opposite side of the vertical gate structure; and

support circuitry coupled to the photon detection array to support operation of the photon detection array, wherein the support circuitry is disposed in a second semiconductor layer.

12. The photon sensing system of claim 11 , wherein the first semiconductor layer is included in a first semiconductor device wafer, wherein the first semiconductor device wafer is stacked with a second semiconductor device wafer including the second semiconductor layer, and wherein the first and second semiconductor device wafers are coupled together in a stacked chip system.

13. The photon sensing system of claim 11 , wherein the vertical gate structure comprises:
a doped polysilicon filled trench disposed in the first semiconductor layer proximate to the SPAD; and
a passivation layer lining the doped polysilicon filled trench, wherein the passivation layer is disposed between the doped polysilicon inside the trench and semiconductor material of the first semiconductor layer.

14. The photon sensing system of claim 13 , wherein the gate bias voltage is a positive voltage coupled to the doped polysilicon inside the trench, wherein the semiconductor material of the first semiconductor layer outside of the SPAD is coupled to receive a negative operational bias voltage.

15. The photon sensing system of claim 11 , wherein the multiplication junction is reversed biased above a breakdown voltage such that photons directed into the SPAD trigger an avalanche multiplication process in the multiplication junction.

16. The photon sensing system of claim 15 , wherein the SPAD is formed in a front side of the first semiconductor layer, and wherein the SPAD is optically coupled to receive the photons through a back side of the first semiconductor layer.

17. The photon sensing system of claim 11 , wherein the support circuitry disposed in the second semiconductor layer includes quenching circuitry and time to digital converter (TDC) circuitry coupled to the photon detection array.

Assignees

• Omnivision Tech Inc

Inventors

• Zhang Bowei
• Mao Duli

Classifications

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H01L31/02161

  Electricity · mapped topic

• H01L27/1462

  Electricity · mapped topic

• H01L27/1464

  Electricity · mapped topic