Integrated circuit comprising a metal-insulator-metal capacitor and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-10141394-B2
Application number	US-201615360859-A
Country	US
Kind code	B2
Filing date	Nov 23, 2016
Priority date	Nov 25, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

The disclosed technology relates to a metal-insulator-metal capacitor (MIMCAP) integrated as part of a back-end-of-line of an integrated circuit (IC). In one aspect, a MIMCAP comprises a first planar electrode having perforations formed therethrough, and a metal-insulator-metal (MIM) stack lining inner surfaces of cavities formed in the perforations and extending into the substrate. The MIMCAP additionally comprises a second electrode having a planar portion and metal extensions extending from the planar portion into the cavities. The first electrode and the planar portion of the second electrode are formed of or comprise planar metal areas of the respective metallization levels, which can be formed by a damascene process, which allows for a reduction of the series resistance. A low aspect ratio can be obtained using one electrode having a 3D-structure (the electrode having extensions extending into the cavities).

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a semiconductor substrate; and
a plurality of metallization levels, each metallization level comprising a layer of intermetal dielectric having metal areas embedded therein,
a metal-insulator-metal capacitor (MIMCAP) comprising a bottom electrode, a top electrode and a metal-insulator-metal (MIM) stack comprising a lower conductive layer, an upper conductive layer and an insulator layer sandwiched between the lower and upper conductive layers,
wherein the bottom electrode comprises a planar metal area of a lower metallization level, the planar metal area having perforations formed therethrough,
wherein the IC comprises cavities, each cavity extending through one of the perforations and into the semiconductor substrate, each cavity being separated from edges of a corresponding perforation by a first intermetal dielectric material of the lower metallization level,
wherein the MIM stack comprises a planar portion of the MIM stack on at least a part of an upper surface of the bottom electrode and a plurality of non-planar portions of the MIM stack extending into the cavities, the MIM stack lining the sidewalls and bottoms of the cavities, and
wherein the top electrode comprises:
a planar portion of the top electrode formed by a planar metal area of an upper metallization level adjacent to the lower metallization level, wherein the planar portion of the top electrode is formed on at least a part of an upper surface of the planar portion of the MIM stack, and wherein the planar portion of the top electrode has sidewalls lined by portions of the MIM stack, and
non-planar portions of the top electrode extending from the planar portion of the top electrode into the cavities.

2. The IC according to claim 1 , wherein the planar portion of the top electrode comprising a plurality of perforations formed therethrough, each perforation having a central portion formed of a second intermetal dielectric material of the upper metallization level, wherein a side wall of the central portion is surrounded by the MIM stack.

3. The IC according to claim 1 , wherein a portion of the substrate at which the MIMCAP is formed is laterally separated from the remainder of the substrate by a dielectric wall portion enclosing portions of the cavities extending into the substrate.

4. The IC according claim 1 , wherein the bottom electrode further comprises an additional layer of a conductive material on the planar metal area of the lower metallization level, the additional layer being provided with a plurality of perforations corresponding to the perforations formed through the planar metal area.

5. The IC according claim 1 , wherein a portion of the bottom electrode laterally extends beyond the top electrode, and wherein the extended portion of the bottom electrode is contacted by a via connection in the upper metallization level.

6. The IC according to claim 1 , further comprising a power delivery network, and wherein the MIMCAP is a decoupling capacitor coupled between a supply terminal and a ground terminal of the network.

7. The IC according claim 1 , wherein the MIMCAP is a part of a DC/DC converter.

8. The IC according claim 1 , wherein the IC is an interposer chip.

9. The IC according claim 1 , wherein the lower metallization level comprises a first metallization level and the upper metallization level comprises a second metallization level.

Assignees

• Imec Vzw

Inventors

• Detalle Mikael

Classifications

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title