Thin-film transistor array, fabrication method therefor, image display device and display method

Patent metadata

Field	Value
Publication number	US-10141349-B2
Application number	US-201514980314-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Jun 27, 2013
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A thin-film transistor array includes thin-film transistors each including an insulating substrate which is formed with a gate electrode, a gate wiring, a capacitor electrode and a capacitor wiring. A source electrode and a drain electrode having a gap therebetween and including a semiconductor pattern are formed, in a region overlapping with the gate electrode on the substrate via a gate insulator, with the semiconductor pattern being covered with a protective layer. Two such TFTs are independently formed for each pixel. In each pixel, two source electrodes are separately connected to two respective source wirings, and two drain electrodes are connected to an electrode of the pixel via individual drain-connecting electrodes. The array includes source-connecting electrodes each connecting between the source electrodes of the two TFTs formed for each pixel. The same drive waveform is applied to the two source wirings.

First claim

What is claimed is:

1. A thin-film transistor array, comprising:
a plurality of thin-film transistors each having a configuration in which a gate electrode, a gate wiring connected to the gate electrode, capacitor electrode, and a capacitor wiring connected to the capacitor electrode are provided on an insulating substrate, with a source electrode and a drain electrode having a gap therebetween and including a semiconductor pattern being formed, in a region overlapping with the gate electrode via a gate insulator film, the semiconductor pattern being covered with a protective layer, two thin-film transistors of the plurality of thin-film transistors being independently formed for each pixel, two source electrodes in each pixel being separately connected to two respective source wirings, two drain electrodes each being directly connected to an electrode of the pixel via respective drain-connecting electrodes,
wherein the thin-film transistor array includes source-connecting electrodes each connecting between the source electrodes of the two thin-film transistors formed for each pixel,
wherein the protective layer is in a stripe pattern and formed along the gate wirings such that the protective layer covers the semiconductor patterns and the source wirings,
wherein the protective layer does not cover a portion of the source-connecting electrodes, and
wherein the thin-film transistor array includes an insulating film that covers the source wirings and the portion of the source-connecting electrodes not covered by the protective layer.

2. The thin-film transistor array according to claim 1 , wherein the source-connecting electrode has a portion not overlapping with the gate electrode or the gate wiring.

3. The thin-film transistor array according to claim 1 , wherein the protective layer is in a stripe pattern and formed along the gate wirings such that the protective layer covers the semiconductor patterns and the gate wirings.

4. The thin-film transistor array according to claim 1 , wherein each pixel electrode has a first capacitor near the drain electrodes, and a second capacitor remote from the drain electrodes.

5. The thin-film transistor array according to claim 4 , wherein the capacitor electrode has a slit in a region overlapping with the pixel electrode such that the slit divides the capacitor electrode into a first capacitor electrode near drain electrodes, and a second capacitor electrode remote from the drain electrodes,
the first capacitor includes a pixel electrode, a gate insulator film and a first capacitor electrode, and
the second capacitor includes a pixel electrode, a gate insulator film and a second capacitor electrode.

6. The thin-film transistor array according to claim 4 , wherein the insulating film includes an opening formed over the first capacitor portion of the pixel electrode, and
wherein an upper pixel electrode is formed on the insulating film and connected to the pixel electrode via the opening.

7. The thin-film transistor array according to claim 1 , wherein a portion of each drain electrode is perpendicular to the respective drain-connecting electrode.

Assignees

• Toppan Printing Co Ltd

Inventors

• Ishizaki Mamoru

Classifications

• G02F2001/136272

  Physics · mapped topic

• G09G3/3688

  suitable for active matrices only · CPC title

• G02F1/136259

  Repairing; Defects · CPC title

• G02F2201/50

  Protective arrangements · CPC title

• G09G2320/0204

  Compensation of DC component across the pixels in flat panels · CPC title