Manufacturing method of interconnection structure

Patent metadata

Field	Value
Publication number	US-10141224-B2
Application number	US-201715821666-A
Country	US
Kind code	B2
Filing date	Nov 22, 2017
Priority date	Mar 10, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first surface and a second surface opposite to each other is provided. Then, a conductive through via extended from the first surface to the second surface is formed in the substrate. Then, a portion of the substrate is removed from the first surface to expose a portion of the conductive through via. Then, a dielectric layer is formed on the substrate, and the dielectric layer covers the exposed conductive through via. Then, an opening is formed in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and the top surface of the conductive through via protrudes from the bottom surface of the opening. Then, a conductive layer is formed in the opening.

First claim

What is claimed is:

1. A manufacturing method of an interconnection structure, comprising:
providing a substrate;
forming a conductive through via in the substrate, wherein the substrate has a first surface and a second surface opposite to each other, and the conductive through via is extended from the first surface to the second surface;
removing a portion of the substrate from the first surface to expose a portion of the conductive through via;
forming a dielectric layer on the substrate, wherein the dielectric layer covers the exposed conductive through via;
forming an opening in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and a top surface of the conductive through via protrudes from a bottom surface of the opening; and
forming a conductive layer in the opening, wherein the conductive layer comprises a seed layer and a conductive material layer and top surfaces of the seed layer and the conductive material layer are respectively aligned with a top surface of the dielectric layer,
wherein a method of forming the conductive layer comprises:
forming the seed layer on the dielectric layer;
performing an electroplating process to form the conductive material layer on the seed layer, wherein the opening is completely filled with the conductive material layer; and
removing a portion of the conductive material layer and keeping the conductive material layer located in the opening to form the conductive layer.

2. The method of claim 1 , wherein after a portion of the substrate is removed from the first surface, the top surface of the conductive through via is higher than the first surface by 1 μm to 50 μm.

3. The method of claim 1 , wherein a method of removing a portion of the substrate from the first surface comprises performing a wet etching process.

4. The method of claim 1 , wherein a method of forming the opening comprises performing a laser drilling process or performing a patterning process.

5. The method of claim 1 , further comprising, before a portion of the substrate is removed from the first surface, forming a protective layer on the second surface.

6. The method of claim 5 , further comprising, after the conductive layer is formed, removing the protective layer.

Assignees

• Unimicron Technology Corp

Inventors

• Hu Dyi-Chung
• Hung Yin-Po
• Tain Ra-Min
• Chen Yu-Hua

Classifications

• H10W70/635 Primary

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/057 Primary

  by selectively depositing, e.g. by using selective CVD or plating · CPC title