Array substrate, display panel and display apparatus having the same, and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-10141154-B2
Application number	US-201715786479-A
Country	US
Kind code	B2
Filing date	Oct 17, 2017
Priority date	May 13, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

The present application discloses an array substrate comprising a first substrate, a first electrode on the first substrate, a passivation layer on a side of the first electrode distal to the first substrate, the passivation layer comprising a plurality of first vias, each of which corresponds to a different part of the first electrode, an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias, and a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias. The at least one electron emission source comprises a first portion having a first end and a second portion having a second end. The first end is in contact with the first electrode, the first portion is within a corresponding one of the plurality of dielectric blocks. The second portion and the second end are outside the corresponding one of the plurality of dielectric blocks.

First claim

What is claimed is:

1. An array substrate, comprising:
a first substrate;
a first electrode on the first substrate;
a passivation layer on a side of the first electrode distal to the first substrate, the array substrate comprising a plurality of first vias in the passivation layer, each of which corresponds to a different part of the first electrode;
an electron emission source layer on a side of the first electrode distal to the first substrate comprising at least one electron emission source in each of the plurality of first vias; and
a dielectric layer on a side of the first electrode distal to the first substrate comprising a plurality of dielectric blocks corresponding to the plurality of first vias, at least a portion of each of the plurality of dielectric blocks in each of the plurality of first vias;
wherein the at least one electron emission source comprises a first portion having a first end and a second portion having a second end;
the first end is in contact with the first electrode, the first portion is within a corresponding one of the plurality of dielectric blocks;
the second portion and the second end are outside the corresponding one of the plurality of dielectric blocks; and
the dielectric layer is made of a material consisting essentially of a resin.

2. The array substrate of claim 1 , further comprising an electron absorption layer on a side of the passivation layer distal to the first electrode, the array substrate comprising a plurality of second vias in the electron absorption layer, each of which corresponds to a corresponding one of the plurality of first vias.

3. The array substrate of claim 2 , wherein an orthographic projection of each of the plurality of second vias on the first substrate substantially covers an orthographic projection of the corresponding one of the plurality of first vias.

4. The array substrate of claim 2 , wherein the electron absorption layer is a ground metal layer or a grid electrode plate.

5. The array substrate of claim 1 , further comprising:
a gate electrode on the first substrate;
a gate insulating layer on a side of the gate electrode distal to the first substrate;
an active layer on a side of the gate insulating layer distal to the first substrate; and
a source electrode and a drain electrode on a side of the active layer distal to the first substrate;
wherein the first electrode is on a side of the gate insulating layer distal to the first substrate, and is connected to the drain electrode.

6. The array substrate of claim 1 , wherein the at least one electron emission source has a one-dimensional or quasi-one-dimensional structure.

7. The array substrate of claim 1 , wherein the at least one electron emission source is a nano-structure having a shape selected from a group consisting of a rod, a wire, and a cone.

8. The array substrate of claim 7 , wherein the at least one electron emission source is made of one or a combination of a carbon nano-tube and a semiconductor oxide.

9. The array substrate of claim 8 , wherein the carbon nano-tube is a doped carbon nano-tube, and the semiconductor oxide is a doped semiconductor oxide.

10. A display panel, comprising the array substrate of claim 1 , a second substrate facing the first substrate; a second electrode on a side of the second substrate proximal to the first substrate; a phosphor layer on a side of the second electrode proximal to the first substrate.

11. The display panel of claim 10 , further comprising a spacer between the first substrate and the second substrate.

12. The display panel of claim 11 , wherein the spacer is in a same layer as the dielectric layer.

13. A display apparatus comprising a display panel of claim 10 .

14. The array substrate of claim 1 , wherein the dielectric layer is made of a material consisting of a resin.

15. The array substrate of claim 1 , wherein the dielectric layer and the passivation layer comprise a same material.

16. The array substrate of claim 1 , wherein the dielectric layer and the passivation layer are made of a material consisting essentially of a resin.

17. The display panel of claim 10 , wherein the array substrate further comprises an electron absorption layer on a side of the passivation layer distal to the first electrode and configured to absorb electrons emitted from electron emission sources along a direction away from corresponding pixel area in the phosphor layer, the electron absorption layer comprising a plurality of second vias, each of which corresponds to a corresponding one of the plurality of first vias.

18. The display panel of claim 11 , wherein the dielectric layer and the spacer comprise a same material.

19. The display panel of claim 11 , wherein the dielectric layer and the spacer are made of a material consisting essentially of a resin.

20. The display panel of claim 11 , wherein the dielectric layer, the passivation layer, and the spacer are made of a material consisting essentially of a resin.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Bao Zhiying
• Chen Xiaochuan
• Jiang Wenbo
• Wang Shijun
• Wang Lei
• Li Yue
• Xue Yanna
• Lv Zhenhua
• Xiao Wenjun
• Zhang Yong

Classifications

• H01L27/1248

  Electricity · mapped topic

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• H01J31/127

  using large area or array sources, i.e. essentially a source for each pixel group · CPC title

• H01J2209/0223

  Field emission cathodes · CPC title

• H01J9/025

  of field emission cathodes · CPC title