Laminated electronic component and mounting structure thereof

Patent metadata

Field	Value
Publication number	US-10141112-B2
Application number	US-201515325193-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Jul 30, 2014
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A laminated electronic component includes: a rectangular parallelepiped-shaped stacked body including dielectric layers and internal electrode layers which are alternately laminated; and a pair of first conductors and a pair of second conductors which are disposed on an outer surface of the stacked body. The first conductors are disposed in portions which include centers of long sides of a first principal surface which is positioned in a direction of lamination of the dielectric layers and the internal electrode layers of the stacked body, and do not include a vertex of the stacked body so as to extend from first side surfaces to the first principal surface. The second conductors are disposed on second side surfaces, and the first conductors and the second conductors are spaced apart from each other on an outer surface and electrically connected to each other via the internal electrode layers.

First claim

The invention claimed is:

1. A laminated electronic component comprising:
a stacked body having a rectangular parallelepiped shape, the stacked body comprising dielectric layers and internal electrode layers which are alternately laminated; and
a pair of first conductors and a pair of second conductors disposed on an outer surface of the stacked body,
the stacked body comprising a pair of first and second principal surfaces which has a rectangular shape and is positioned in a direction of lamination of the dielectric layers and the internal electrode layers, a pair of first side surfaces adjacent to long sides of the pair of first and second principal surfaces, and a pair of second side surfaces adjacent to short sides of the pair of first and second principal surfaces,
the pair of first conductors being disposed in portions which include centers of the short sides of the first principal surface, and do not include the second principal surface and a vertex of the stacked body, and the pair of first conductors comprising side surface sections which extend from the short sides on the pair of second side surfaces, and projection sections which extend from the short sides on the first principal surface,
the pair of second conductors being disposed on the pair of first side surfaces or the pair of second side surfaces, and
the pair of first conductors and the pair of second conductors being spaced apart from each other on the outer surface and electrically connected to each other via the internal electrode layers,
in the direction of lamination of the dielectric layers and the internal electrode layers, a ratio of a length of each of the side surface sections of the pair of first conductors to a length of the stacked body is equal to or less than 0.4,
wherein when a length of the long sides is denoted by L and a length of the pair of first conductors along the short sides is denoted by W, a ratio of W to L is equal to or less than 0.35.

2. The laminated electronic component according to claim 1 , wherein the side surface sections of the pair of first conductors, and the pair of second conductors are respectively disposed on different side surfaces among the pair of first side surfaces and the pair of second side surfaces.

3. The laminated electronic component according to claim 1 , wherein the side surface sections of the pair of first conductors and the pair of second conductors are disposed on one of the pair of first side surfaces and the pair of second side surfaces.

4. The laminated electronic component according to claim 1 , wherein the pair of second conductors is disposed over an entirety in the direction of lamination of the pair of first side surfaces or the pair of second side surfaces.

5. A mounting structure, comprising:
the laminated electronic component according to claim 1 ; and
a substrate which is joined with the projection sections of the pair of first conductors of the laminated electronic component.

Assignees

• Kyocera Corp

Inventors

• Nishimura Michiaki
• Shigenaga Yasuhisa

Classifications

• H05K2201/10015

  Non-printed capacitor · CPC title

• H01G4/005

  Electrodes · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title