Pixel driving circuit, driving method, array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-10140928-B2
Application number	US-201414771349-A
Country	US
Kind code	B2
Filing date	Oct 24, 2014
Priority date	Jul 22, 2014
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

Provided are a pixel driving circuit, a driving method, an array substrate and a display apparatus. The pixel circuit comprises: a data line, a gate line, a first power line, a second power line, a reference signal line, a light emitting device, a driving transistor, a storage capacitor, a reset unit, a data writing unit, a compensation unit and a light emitting control unit. The pixel driving circuit can compensate and eliminate the display nonuniformity caused by the threshold voltage difference of the driving transistors.

First claim

What is claimed is:

1. A pixel driving circuit, comprising: a data line, a gate line, a first power line, a second power line, a reference signal line, a light emitting device, a driving transistor, a storage capacitor, a reset subcircuit, a data writing subcircuit, a compensation subcircuit and a light emitting control subcircuit, wherein:
the data line is configured to provide a data voltage;
the gate line is configured to provide a scanning voltage;
the first power line is configured to provide a first power voltage, the second power line is configured to provide a second power voltage, and the reference signal line is configured to provide a reference voltage;
the reset subcircuit is connected with two terminals of the storage capacitor, and also with the first power line, and the reset subcircuit is configured to reset a voltage across the two terminals of the storage capacitor to a predetermined signal voltage;
the data writing subcircuit is connected with the gate line, the data line and a second terminal of the storage capacitor, and the data writing subcircuit is configured to write information comprising the data voltage to the second terminal of the storage capacitor,
the compensation subcircuit is connected with a first terminal of the storage capacitor and the driving transistor, and the compensation subcircuit is configured to write information comprising a threshold voltage of the driving transistor and the first power voltage to the first terminal of the storage capacitor;
the light emitting control subcircuit is connected with the reference signal line, the second terminal of the storage capacitor, the driving transistor and the light emitting device, and the light emitting control subcircuit is configured to write the reference voltage to the second terminal of the storage capacitor;
the first terminal of the storage capacitor is connected with a gate of the driving transistor, and the storage capacitor is configured to transfer information comprising the data voltage to the gate of the driving transistor; and
the driving transistor is connected with the first power line, the light emitting device is connected with the second power line, and the driving transistor is configured to drive the light emitting device to emit light, wherein the reset subcircuit comprises a reset control line, a reset signal line, a first transistor and a second transistor, a gate of the first transistor and a gate of the second transistor are both connected with the reset control line, a source of the first transistor is connected with the reset signal line, a drain of the first transistor is connected with the first terminal of the storage capacitor, a source of the second transistor is connected with the first power line, a drain of the second transistor is connected with the second terminal of the storage capacitor, and the first transistor and the second transistor are respectively configured to write the voltage of the reset signal line to the first terminal of the storage capacitor and to write the first power voltage to the second terminal of the storage capacitor both under control of the reset control line, wherein the reset signal line, the first power line and the reference signal line are three different signal lines, and the voltage of the reset signal line is a low voltage and is different from the first power voltage of the first power line and is different from the reference voltage of the reference signal line.

2. The pixel driving circuit according to claim 1 , wherein both the first transistor and the second transistor are P type transistors.

3. The pixel driving circuit according to claim 1 , wherein the data writing subcircuit comprises a fourth transistor, a gate of the fourth transistor is connected with the gate line, a source of the fourth transistor is connected with the data line, a drain of the fourth transistor is connected with the second terminal of the storage capacitor, and the fourth transistor is configured to write the data voltage to the second terminal of the storage capacitor.

4. The pixel driving circuit according to claim 3 , wherein the fourth transistor is a P type transistor.

5. The pixel driving circuit according to claim 1 , wherein the compensation subcircuit is also connected with the gate line, and the compensation subcircuit comprises a third transistor, a gate of the third transistor is connected with the gate line, a source of the third transistor is connected with the first terminal of the storage capacitor, a drain of the third transistor is connected with a drain of driving transistor, and the third transistor is configured to write information comprising the threshold voltage of the driving transistor and the first power voltage to the first terminal of the storage capacitor.

6. The pixel driving circuit according to claim 5 , wherein the third transistor is a P type transistor.

7. The pixel driving circuit according to claim 1 , wherein the light emitting control subcircuit comprises a light emitting control line, a fifth transistor and a sixth transistor; a gate of the fifth transistor is connected with the light emitting control line, a source of the fifth transistor is connected with the reference signal line, a drain of the fifth transistor is connected with the second terminal of the storage capacitor, and the fifth transistor is configured to write the reference voltage to the second terminal of the storage capacitor, and the reference voltage is transferred to the gate of the driving transistor by the storage capacitor; a gate of the sixth transistor is connected with the light emitting control line, a source of the sixth transistor is connected with a first terminal of the light emitting device, a drain of the sixth transistor is connected with the drain of the driving transistor, and the sixth transistor is configured to control the light emitting device to emit light; and the driving transistor is configured to drive the light emitting device to emit light under the control of the light emitting control subcircuit.

8. The pixel driving circuit according to claim 7 , wherein the driving transistor, the fifth transistor and the sixth transistor are P type transistors.

9. The pixel driving circuit according to claim 1 , wherein the reference signal line and the first power line are arranged to be parallel with each other.

10. The pixel driving circuit according to claim 9 , wherein a width of the first power line is greater than that of the reference signal line.

11. The pixel driving circuit according to claim 1 , wherein the reset signal line and the first power line are arranged to be parallel with each other.

12. The pixel driving circuit according to claim 11 , wherein a width of the first power line is greater than that of the reset signal line.

13. A method for driving a pixel driving circuit, wherein the pixel driving circuit comprises: a data line, a gate line, a first power line, a second power line, a reference signal line, a light emitting device, a driving transistor, a storage capacitor, a reset subcircuit, a data writing subcircuit, a compensation subcircuit and a light emitting control subcircuit, wherein:
the data line is configured to provide a data voltage;
the gate line is configured to provide a scanning voltage;
the first power line is configured to provide a first power voltage, the second power line is configured to provide a second power voltage, and the reference signal line is configured to provide a reference voltage;
the reset subcircuit is connected with two terminals of the storage capacitor, and also with the first power line, and the reset subcircuit is configured to reset

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Ying
• Yin Xinshe
• Sun Liang

Classifications

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G3/3283 Primary

  in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title