Hierarchical scalable neuromorphic synaptronic system for synaptic and structural plasticity

Patent metadata

Field	Value
Publication number	US-10140571-B2
Application number	US-201615280027-A
Country	US
Kind code	B2
Filing date	Sep 29, 2016
Priority date	Jan 27, 2012
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

In one embodiment, the present invention provides a neural network circuit comprising multiple symmetric core circuits. Each symmetric core circuit comprises a first core module and a second core module. Each core module comprises a plurality of electronic neurons, a plurality of electronic axons, and an interconnection network comprising multiple electronic synapses interconnecting the axons to the neurons. Each synapse interconnects an axon to a neuron. The first core module and the second core module are logically overlayed on one another such that neurons in the first core module are proximal to axons in the second core module, and axons in the first core module are proximal to neurons in the second core module. Each neuron in each core module receives axonal firing events via interconnected axons and generates a neuronal firing event according to a neuronal activation function.

First claim

What is claimed is:

1. A method comprising:
receiving a first firing event generated by a first symmetric core circuit of a plurality of symmetric core circuits, wherein the plurality of symmetric core circuits are interconnected via a plurality of routers, each router corresponds to a symmetric core circuit of the plurality of symmetric core circuits, and each router comprises a compact lookup table (LUT) maintaining routing information for each firing event generated by a corresponding symmetric core circuit;
retrieving routing information for the first firing event from a first router of the plurality of routers, wherein the first router corresponds to the first symmetric core circuit;
generating a first packet for the first firing event based on the routing information retrieved; and
routing the first packet between the plurality of symmetric core circuits via the plurality of routers,
wherein each symmetric core circuit comprises a first core module and a second core module overlaid on one another and oriented differently relative to each other such that neurons and axons of the first core module are overlaid on and within proximity of axons and neurons of the second core module, respectively, and firing events propagate through the first core module and the second core module in opposite directions.

2. The method of claim 1 , wherein each symmetric core circuit comprises a plurality of electronics neurons interconnected to a plurality of electronic axons via a plurality of electronic synapses.

3. The method of claim 2 , wherein each packet for each firing event is routed to a target axon of a symmetric core circuit of the plurality of symmetric core circuits.

4. The method of claim 3 , wherein routing information for a firing event comprises at least one of: a distance to a target axon, a direction to the target axon, an address of the target axon, and a delivery time indicative of a time a packet for the firing event is scheduled for delivery to the target axon.

5. The method of claim 4 , wherein the plurality of symmetric core circuits are organized into multiple regions, each region comprising a group of axons representing a fascicle.

6. The method of claim 5 , wherein each LUT of each router is compact as the router routes outgoing packets to and receives incoming packets from a same region of the plurality of symmetric core circuits, such that the outgoing packets traverse an identical route but are delivered to different target axons of the same region.

7. The method of claim 6 , wherein a compact LUT allows one or more parametrized chip compiler variants to be generated on the fly.

8. A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising:
receiving a first firing event generated by a first symmetric core circuit of a plurality of symmetric core circuits, wherein the plurality of symmetric core circuits are interconnected via a plurality of routers, each router corresponds to a symmetric core circuit of the plurality of symmetric core circuits, and each router comprises a compact lookup table (LUT) maintaining routing information for each firing event generated by a corresponding symmetric core circuit;
retrieving routing information for the first firing event from a first router of the plurality of routers, wherein the first router corresponds to the first symmetric core circuit;
generating a first packet for the first firing event based on the routing information retrieved; and
routing the first packet between the plurality of symmetric core circuits via the plurality of routers;
wherein each symmetric core circuit comprises a first core module and a second core module overlaid on one another and oriented differently relative to each other such that neurons and axons of the first core module are overlaid on and within proximity of axons and neurons of the second core module, respectively, and firing events propagate through the first core module and the second core module in opposite directions.

9. The system of claim 8 , wherein each symmetric core circuit comprises a plurality of electronics neurons interconnected to a plurality of electronic axons via a plurality of electronic synapses.

10. The system of claim 9 , wherein each packet for each firing event is routed to a target axon of symmetric core circuit of the plurality of symmetric core circuits.

11. The system of claim 10 , wherein routing information for a firing event comprises at least one of: a distance to a target axon, a direction to the target axon, an address of the target axon, and a delivery time indicative of a time a packet for the firing event is scheduled for delivery to the target axon.

12. The system of claim 11 , wherein the plurality of symmetric core circuits are organized into multiple regions, each region comprising a group of axons representing a fascicle.

13. The system of claim 12 , wherein each LUT of each router is compact as the router routes outgoing packets to and receives incoming packets from a same region of the plurality of symmetric core circuits, such that the outgoing packets traverse an identical route but are delivered to different target axons of the same region.

14. The system of claim 13 , wherein a compact LUT allows one or more parametrized chip compiler variants to be generated on the fly.

15. A computer program product comprising a computer-readable hardware storage device having program code embodied therewith, the program code being executable by a computer to implement a method comprising:
receiving a first firing event generated by a first symmetric core circuit of a plurality of symmetric core circuits, wherein the plurality of symmetric core circuits are interconnected via a plurality of routers, each router corresponds to a symmetric core circuit of the plurality of symmetric core circuits, and each router comprises a compact lookup table (LUT) maintaining routing information for each firing event generated by a corresponding symmetric core circuit;
retrieving routing information for the first firing event from a first router of the plurality of routers, wherein the first router corresponds to the first symmetric core circuit;
generating a first packet for the first firing event based on the routing information retrieved; and
routing the first packet between the plurality of symmetric core circuits via the plurality of routers,
wherein each symmetric core circuit comprises a first core module and a second core module overlaid on one another and oriented differently relative to each other such that neurons and axons of the first core module are overlaid on and within proximity of axons and neurons of the second core module, respectively, and firing events propagate through the first core module and the second core module in opposite directions.

16. The computer program product of claim 15 , wherein each symmetric core circuit comprises a plurality of electronics neurons interconnected to a plurality of electronic axons via a plurality of electronic synapses.

17. The computer program product of claim 16 , wherein each packet for each firing event is routed to a target axon of a symmetric core circuit of the plurality of symmetric core circuits.

18. The computer program product of claim 17 , wherein routing information for a firing event comprises at least one of: a distance to a target axon, a direction to the target axon, an address of the target axon,

Assignees

• IBM

Inventors

• Modha Dharmendra S

Classifications

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06F17/30979

  Physics · mapped topic

• G06N3/049

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/06

  Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons · CPC title

• G06N3/061

  using biological neurons, e.g. biological neurons connected to an integrated circuit · CPC title