Analog processor comprising quantum devices

Patent metadata

Field	Value
Publication number	US-10140248-B2
Application number	US-201715635735-A
Country	US
Kind code	B2
Filing date	Jun 28, 2017
Priority date	Dec 23, 2004
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices. A method of determining a result of a computational problem using an analog processor includes receiving at a first digital computer, including a digital processor, an instance of the computational problem defined over an input graph, wherein the input graph is non-planar; and determining a mapping of the instance of the computational problem onto the analog processor, by the digital processor.

First claim

We claim:

1. A method of determining a result of a computational problem using an analog processor, comprising:
receiving at a first digital computer, including a digital processor, an instance of the computational problem defined over an input graph, wherein the input graph is non-planar; and
determining a mapping of the instance of the computational problem onto the analog processor, by the digital processor.

2. The method of claim 1 , wherein the analog processor comprises a plurality of quantum devices, a plurality of readout devices associated with the plurality of quantum devices, and a plurality of coupling devices selectively operable to tunably couple pairs of quantum devices in the plurality of quantum devices, the method comprises:
setting a state of at least one quantum device in the plurality of quantum devices, by the digital processor;
setting a coupling strength of at least one of the coupling devices in the plurality of coupling devices to an initial state, by the digital processor;
causing the analog processor to evolve toward a final state, by the digital processor; and
reading out a final state of at least one quantum device in the plurality of quantum devices via the at least one readout device in the plurality of readout devices to determine a result of the computational problem, by the digital processor.

3. The method of claim 2 , further comprising returning the result of the computational problem, by the digital processor.

4. The method of claim 2 , wherein causing the analog processor to evolve toward the final state by the digital processor includes:
by the digital processor evolving, by the digital processor, the analog processor adiabatically.

5. The method of claim 4 wherein causing a decrease in an effective temperature of the analog processor includes raising a barrier height of at least one quantum device in the plurality of quantum devices, and causing an increase in the effective temperature of the analog processor includes lowering the barrier height of at least one quantum device in the plurality of quantum devices.

6. The method of claim 2 , wherein causing the analog processor to evolve toward the final state by the digital processor includes:
causing an increase of a temperature of the analog processor from a base temperature, by the digital processor, and then causing a decrease in the temperature of the analog processor toward the base temperature, by the digital processor.

7. The method of claim 2 , wherein causing the analog processor to evolve toward the final state by the digital processor includes:
evolving, by the digital processor, the analog processor adiabatically.

8. The method of claim 1 , further comprising returning the mapping of the instance of the computational problem onto the analog processor.

9. The method of claim 1 , wherein the analog processor comprises a plurality of quantum devices arranged in a lattice, and determining a mapping of the instance of the computational problem onto the analog processor includes determining a mapping of the instance of the computational problem onto the plurality of quantum devices arranged in the lattice, the method further comprising embedding the instance of the computational problem into the lattice, by the digital processor.

10. The method of claim 9 , wherein the input graph of the instance of the computational problem is a graph selected from the group consisting of an expansion of K 5 , and an expansion of K 3,3 .

11. The method of claim 9 , wherein the instance of the computational problem comprises a plurality of variables, the method further comprising:
associating a first variable in the plurality of variables with a first quantum device in the plurality of quantum devices;
associating a second variable in the plurality of variables with a second quantum device in the plurality of quantum devices, wherein the first quantum device and the second quantum device are nearest neighbors in the lattice; and
associating a third variable in the plurality of variables with a third quantum device in the plurality of quantum devices, wherein the first quantum device and the third quantum device are next-nearest neighbors in the lattice.

12. The method of claim 1 wherein the analog processor comprises a plurality of quantum devices and a plurality of local bias devices associated with the plurality of quantum devices, and determining a mapping of the instance of the computational problem onto the analog processor includes determining a mapping of the instance of the computational problem onto the plurality of quantum devices, the method further comprising:
setting, by the digital processor, a local bias value for at least one quantum device in the plurality of quantum devices via at least one local bias device in the plurality of local bias devices.

13. The method of claim 1 , wherein the analog processor comprises a plurality of quantum devices, a plurality of readout devices associated with the plurality of quantum devices, and a plurality of coupling devices selectively operable to tunably couple pairs of quantum devices in the plurality of quantum devices, and determining a mapping of the instance of the computational problem onto the analog processor includes determining a mapping of the instance of the computational problem onto the plurality of quantum devices and the plurality of coupling devices.

Assignees

• D Wave Systems Inc

Inventors

• Maassen Van Den Brink Alexander
• Love Peter
• Amin Mohammad H S
• Rose Geordie
• Grant David
• Steininger Miles F H
• Bunyk Paul I
• Berkley Andrew J

Classifications

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• G06F15/80 Primary

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• H04L67/12

  specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title