Multi-processor non-volatile memory system having a lockless flow data path

Patent metadata

Field	Value
Publication number	US-10140036-B2
Application number	US-201615169117-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	Oct 29, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A system and method is disclosed for managing a non-volatile memory system having a multi-processor controller. The controller may be configured with a plurality of processors and a shared data queue in a cyclic data buffer. Each of the plurality of processors may manage a separate pointer pointing to a different entry of the shared data queue and multiple ones of the processors may concurrently access or update entries in the shared data queue.

First claim

We claim:

1. A method for managing operations in a non-volatile memory system having a controller with a plurality of processors and a data path queue shared by the plurality of processors, the method comprising:
a first processor of the plurality of processors in the controller inserting host command data for a received host command at a first entry location of the shared data path queue;
the first processor updating a first pointer to point to a next entry location adjacent to the first entry location in the shared data path queue after inserting the host command data at the first entry location;
a second processor of the plurality of processors in the controller accessing data in a different entry location in the shared data path queue, and executing an operation in the non-volatile memory system relating to the accessed data in the different entry location in the shared data path queue, concurrently with the first processor inserting the host command data at the first entry location;
when the first pointer is not pointing to a second next entry location in the shared data path queue immediately adjacent to the different entry location, the second processor updating a second pointer to point to the second next entry location;
when the first pointer is pointing to the second next entry location in the shared data path queue, the second processor waiting until the first pointer moves away from the second next data entry location before updating the second pointer to point to the second next entry location; and
updating data in the first entry location to include a physical storage location in a non-volatile memory of the non-volatile memory system.

2. The method of claim 1 , wherein the shared data path queue is stored in a cyclic data buffer.

3. The method of claim 2 , wherein updating the first pointer and updating the second pointer comprises the first processor only moving the first pointer in a single direction along the cyclic data buffer and the second processor only moving the second pointer in the single direction along the cyclic data buffer.

4. The method of claim 1 , further comprising the first processor transmitting a message to the second processor after updating the first pointer.

5. The method of claim 1 , wherein the received host command is a write command and wherein the method further comprises, when the second pointer points to the first entry location, the second processor reading the write command from the first entry location and writing data associated with a logical block address included in the write command to the non-volatile memory.

6. The method of claim 5 , wherein the updating of the data in the first entry location to include the physical storage location in the non-volatile memory is performed by the second processor upon writing the data associated with the logical block address to the non-volatile memory.

7. The method of claim 1 , wherein the received host command is a read command and wherein the method further comprises:
when the second pointer points to the first entry location, the second processor reading the read command from the first entry location and transmitting a message to a third processor of the plurality of processors; and
when a third pointer associated with the third processor reaches the first entry location, the third processor retrieving from a mapping table a physical location of data associated with a logical block address in the read command.

8. A non-volatile memory system comprising:
a non-volatile memory;
a shared data path queue for host commands, the shared data path queue having a plurality of entry locations;
a controller in communication with the non-volatile memory and the shared data path queue, the controller comprising:
a plurality of processors, wherein each of the plurality of processors is configured to:
exclusively control a respective data path queue pointer pointing to a respective one of the plurality of entry locations;
operate on, or update, a respective host command in an entry location currently pointed to by its respective data path queue pointer; and
after operating on or updating the respective host command, update its respective data path queue pointer to point to a next entry location in the shared data path queue only when the next entry location is not already being pointed to by another data path queue pointer;
wherein each of the plurality of processors is configured to concurrently operate on different host commands in different ones of the plurality of entry locations in the shared data path queue; and
wherein at least one of the plurality of processors is configured to update data in one of the plurality of entry locations to include a physical storage location in the non-volatile memory.

9. The non-volatile memory system of claim 8 , wherein the shared data path queue is stored in a cyclic data buffer.

10. The non-volatile memory system of claim 9 , wherein each of the plurality of processors is configured to only update its respective data path queue pointer in a same single direction of the circular data buffer.

11. The non-volatile memory system of claim 10 , wherein the next entry location comprises an entry location adjacent to a current entry location being pointed to by the respective data path queue in the same single direction.

12. The non-volatile memory system of claim 9 , further comprising a volatile memory wherein the cyclic data buffer and each respective data path queue pointer are maintained in the volatile memory.

13. The non-volatile memory system of claim 8 , wherein the non-volatile memory comprises a silicon substrate and a plurality of memory cells forming a monolithic three-dimensional structure, wherein at least one portion of the memory cells is vertically disposed with respect to the silicon substrate.

14. The non-volatile memory system of claim 10 , wherein a first processor of the plurality of processors, the first processor having a first data path queue pointer, is configured to, in response to receipt of a host write command, insert the host write command into a first entry location in the data path queue.

15. The non-volatile memory system of claim 14 , wherein a second processor of the plurality of processors is configured to, after the first processor has moved the first data path queue pointer from the first entry location:
move a second data path queue pointer associated with the second processor to point to the first entry location; and
write data associated with the host write command of the first entry location to the non-volatile memory.

16. The non-volatile memory system of claim 15 , wherein a third processor of the plurality of processors is configured to, after the second processor has moved the second data path queue pointer from the first entry location:
move a third data path queue pointer associated with the third processor to point to the first entry location; and
update a mapping table with logical-to-physical mapping information for the data associated with the host write command.

17. A method for managing operations in a non-volatile memory system having a non-volatile memory, a controller in communication with the non-volatile memory and having a plurality of processors, and a data path queue for host commands, the data path queue shared by the plurality of processors, the method comprising:
a first processor of the plurality of processors in the controller performing a first operation relating to a first host command at a first entry location of the shared data path queue;
after performing the first oper

Assignees

• Sandisk Technologies Llc

Inventors

• Kelner Vered
• Deshe Noga
• Banin Alon
• Vishne Gadi
• Zagalsky Yevgeny
• Gusev Ilya
• Abou Eran Ben

Classifications

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title