Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints

Patent metadata

Field	Value
Publication number	US-10139889-B2
Application number	US-201514998158-A
Country	US
Kind code	B2
Filing date	Dec 24, 2015
Priority date	Mar 15, 2013
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.

First claim

What is claimed is:

1. A system on a chip (SoC) comprising:
a multicore processor;
a level-2 (L2) cache controller coupled to the multicore processor;
an L2 cache coupled to the L2 cache controller and the multicore processor;
an integrated memory controller; and
a serial point-to-point link interface to enable between the multicore processor and a device communication;
wherein the serial point-to-point link interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream from the device;
wherein the protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device;
wherein the protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device;
wherein, in response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of the default recovery time to complete the transition; and
wherein the active state is an uninitialized active state and accessing the device prior to expiration of the default recovery time to complete the transition comprises sending a configuration access request.

2. The SoC of claim 1 , wherein the protocol stack is a peripheral component interconnect express (PCIe) protocol stack and the device is a PCIe endpoint device.

3. The SoC of claim 2 , wherein the configuration access request comprises a configuration access request according to a PCIe-based protocol.

4. The SoC of claim 1 , wherein the indication is based on an expiration of a recovery time specified in a register of the device.

5. The SoC of claim 1 , wherein the indication is based on an interrupt received from the device.

Assignees

• Intel Corp

Inventors

• Wagh Mahesh
• Gough Robert E

Classifications

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• H04L49/15

  Interconnection of switching modules · CPC title

• G06F1/325

  Power saving in peripheral device · CPC title