High speed I/O pinless structural testing

Patent metadata

Field	Value
Publication number	US-10139445-B2
Application number	US-201615282030-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A technical solution for improving test times and costs associated with IC production includes a central test engine (CTE) functional test block integrated onto an IC. The CTE functions as a hardware abstraction layer (HAL), and provides testing capabilities by transferring a large test data file to a device under test and performing a closed-loop monitoring of receipt of the expected test data results. The CTE also reduces the number of external interfaces and interface controllers used during testing. The reduction in external interfaces reduces the size of the IC, which enables smaller and more efficient IC manufacturing, and may be used to improve small form-factor high-volume manufacturing (HVM). This reduction in IO pins also enables significant reduction in IO resources (e.g., IO drivers) within the IC, and reduces or eliminates IO test hardware dependencies.

First claim

The invention claimed is:

1. A system comprising:
an integrated circuit disposed on a substrate;
a physical layer interface to convey physical medium data between the integrated circuit and a physical medium, the physical layer interface disposed on the substrate;
a central test engine to test the integrated circuit, the central test engine disposed on the substrate; and
a central test engine shim to control the integrated circuit based on test control data received from the central test engine, the central test engine shim disposed on the substrate.

2. The system of claim 1 , further including a control and status register to receive a register programming input from an external interface.

3. The system of claim 2 , further including a BIOS block to provide a BIOS boot sequence to the integrated circuit.

4. The system of claim 2 , further including a protocol engine to generate a protocol-specific test data file, the test data file used by the central test engine to test the integrated circuit.

5. The system of claim 4 , wherein the protocol engine further verifies a test result data file.

6. The system of claim 5 , wherein the protocol engine further includes a payload generator and checker to generate a system memory storage replica that corresponds to the test data file.

7. The system of claim 6 , wherein the payload generator and checker is further to verify the test result data file.

8. The system of claim 1 , further including an interconnect fabric to convey test control data between the central test engine and the integrated circuit.

9. A method of testing an integrated circuit comprising:
receiving a register programming input from an external interface at a control and status register;
generating a test data set and a test control data set at a central test engine, wherein generating the test control data set is based on the register programming input;
receiving the test data set and the test control data set at a central test engine shim, the central test engine shim and the central test engine disposed on a substrate;
generating a physical medium data set at a physical layer based on the test data set;
sending the physical medium data set from the physical layer to a loopback device;
receiving a result data set from the loopback device at the central test engine; and
verifying the result data set.

10. The method of claim 9 , further including applying a boot sequence from a BIOS block to the physical layer.

11. The method of claim 9 , further including generating a protocol-specific test data file at a protocol engine.

12. The method of claim 9 , further including receiving the BIOS boot sequence from the control and status register at a BIOS command queue register within the BIOS block.

13. At least one non-transitory machine-readable storage medium, comprising a plurality of instructions that, responsive to being executed with processor circuitry of a computer-controlled device, cause the computer-controlled device to:
receive a register programming input from an external interface at a control and status register;
generate a test data set and a test control data set at a central test engine, wherein generating the test control data set is based on the register programming input;
receive the test data set and the test control data set at a central test engine shim, the central test engine shim and the central test engine disposed on a substrate;
generate a physical medium data set at the physical layer based on the test data set;
send the physical medium data set from the physical layer to a loopback device;
receive a result data set from the loopback device at the central test engine; and
verify the result data set.

14. The machine-readable storage medium of claim 13 , the instructions further causing the computer-controlled device to apply a boot sequence from a BIOS block to the physical layer.

15. The machine-readable storage medium of claim 13 , the instructions further causing the computer-controlled device to generate a protocol-specific test data file at a protocol engine.

16. The machine-readable storage medium of claim 15 , the instructions further causing the computer-controlled device to cause the protocol engine to verify the result data set.

17. The machine-readable storage medium of claim 16 , the instructions further causing the computer-controlled device to generate a system memory storage replica based on the test data file at a payload generator and checker.

18. The machine-readable storage medium of claim 17 , the instructions further causing the computer-controlled device to verify the test result data file at the payload generator and checker.

19. The machine-readable storage medium of claim 15 , the instructions further causing the computer-controlled device to control the physical layer through an end-point driver within the protocol engine.

20. The machine-readable storage medium of claim 13 , the instructions further causing the computer-controlled device to receive the BIOS boot sequence from the control and status register at a BIOS command queue register within the BIOS block.

Assignees

• Intel Corp

Inventors

• Teoh Chin Keat
• Chellappan Satheesh
• Ong Lay Cheng
• Tan Terrence Huat Hin

Classifications

• G11C2029/0401

  in embedded memories · CPC title

• G06F9/4403

  Processor initialisation · CPC title

• G11C2029/0403

  during or with feedback to manufacture · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title