Flexible Ethernet chip-to-chip inteface systems and methods

Patent metadata

Field	Value
Publication number	US-10135760-B2
Application number	US-201514824715-A
Country	US
Kind code	B2
Filing date	Aug 12, 2015
Priority date	Jun 30, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A Chip-to-Chip (C2C) interface utilizing Flexible Ethernet (FlexE) includes circuitry configured to provide a packet interface on a single card or over backplane/fabric links between two devices, wherein the circuitry comprises flow control and channelization for the FlexE. Each of the two devices can include any of a Network Processor (NPU), a Fabric Interface Card (FIC), a framer, and a mapper. A rate of the FlexE can be increased to support additional information for the flow control and the channelization.

First claim

What is claimed is:

1. A Chip-to-Chip (C2C) interface utilizing Flexible Ethernet (FlexE), the interface comprising:
circuitry configured to provide the FlexE over links between two devices, wherein the links comprise one of backplane links and fabric links, and wherein the circuitry is configured to provide flow control and channelization for the FlexE,
wherein the flow control comprises information, for each calendar slot, that is inserted in and communicated in one of a reserved area of the FlexE overhead and a management channel of the FlexE overhead.

2. The C2C interface of claim 1 , wherein each of the two devices comprises any of a Network Processor (NPU), a Fabric Interface Card (FIC), a framer, and a mapper.

3. The C2C interface of claim 1 , wherein a rate of the FlexE is increased to support additional information for the flow control and the channelization.

4. The C2C interface of claim 1 , wherein the circuitry, for the channelization, is configured to provide a logical channel that shares one of a single calendar slot and a group of calendar slots.

5. The C2C interface of claim 4 , wherein the logical channel changes on a frame boundary.

6. The C2C interface of claim 4 , wherein information associated with the logical channel is communicated in FlexE overhead.

7. The C2C interface of claim 6 , wherein the information is provided in one of a reserved area and a management channel of the FlexE overhead, wherein the management channel is not used in a C2C application.

8. The C2C interface of claim 6 , wherein a calendar area of the FlexE overhead is repurposed for the information.

9. The C2C interface of claim 6 , wherein the information is provided utilizing one of a defined Operational code and a data block immediately following a frame header.

10. The C2C interface of claim 1 , wherein the circuitry, for the flow control, is configured to provide flow control in a FlexE shim.

11. The C2C interface of claim 10 , wherein the flow control comprises an in-band mechanism for XON-XOFF flow control per calendar slot, and wherein the management channel is not used in a C2C application.

12. A circuit utilizing Flexible Ethernet (FlexE) as a Chip-to-Chip (C2C) interface, the circuit comprising:
circuitry configured to provide packet functionality; and
circuitry configured to provide the FlexE over links between the circuitry configured to provide packet functionality and another device, wherein the links comprise one of backplane links and fabric links, and wherein the circuitry is configured to perform flow control and channelization for the FlexE,
wherein the flow control comprises information, for each calendar slot, that is inserted in and communicated in one of a reserved area of the FlexE overhead and a management channel of the FlexE overhead.

13. The circuit of claim 12 , wherein the circuitry configured to provide packet functionality is configured to provide functionality of any of a Network Processor (NPU), a Fabric Interface Card (FIC), a framer, and a mapper.

14. The circuit of claim 12 , wherein a rate of the FlexE is increased to support additional information for the flow control and the channelization.

15. The circuit of claim 12 , wherein the circuitry configured to provide the FlexE, for the channelization, is configured to provide a logical channel that shares one of a single calendar slot and a group of calendar slots.

16. The circuit of claim 15 , wherein the logical channel changes on a frame boundary.

17. The circuit of claim 15 , wherein information associated with the logical channel is communicated in FlexE overhead.

18. The C2C interface of claim 6 , wherein the information is provided through one of
one of a reserved area of the FlexE overhead and a management channel of the FlexE overhead, wherein the management channel is not used in a C2C application,
a calendar area of the FlexE overhead that is repurposed for the information, and
one of a defined Operational code and a data block immediately following a frame header.

19. The C2C interface of claim 1 , wherein the circuitry, for the flow control, is configured to provide flow control in a FlexE shim.

20. A Chip-to-Chip (C2C) interface method utilizing Flexible Ethernet (FlexE), the method comprising:
providing, via circuitry, the FlexE over links between two devices, wherein the links comprise one of backplane links and fabric links, and wherein the circuitry is configured to perform flow control and channelization for the FlexE,
wherein the flow control comprises information, for each calendar slot, that is inserted in and communicated in one of a reserved area of the FlexE overhead and a management channel of the FlexE overhead.

Assignees

• Ciena Corp

Inventors

• Gareau Sebastien

Classifications

• H04L49/45 Primary

  Arrangements for providing or supporting expansion · CPC title

• H04L49/352

  Gigabit ethernet switching [GBPS] · CPC title

• H04L49/15

  Interconnection of switching modules · CPC title

• H04L49/405 Primary

  Physical details, e.g. power supply, mechanical construction or backplane of ATM switches · CPC title

• Y02D50/30

  Cross-Sectional Technologies · mapped topic