Wideband millimeter-wave frontend integrated circuit

Patent metadata

Field	Value
Publication number	US-10135478-B2
Application number	US-201816005472-A
Country	US
Kind code	B2
Filing date	Jun 11, 2018
Priority date	Apr 10, 2017
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

According to one embodiment, a millimeter-wave (mm-wave) frontend integrated circuit includes an array of mm-wave transceivers, where each of the mm-wave transceivers transmits and receives coherent mm-wave signals with variable amplitudes and phase shifts. The mm-wave frontend IC chip further includes a wideband frequency synthesizer coupled to the mm-wave transceivers. The full-based or wideband frequency synthesizer generates and provides a local oscillator (LO) signal to each of the mm-wave transceivers to enable the mm-wave transceiver to mix, modulate, and/or demodulate mm-wave signals. The array of mm-wave wideband transceivers and the wideband frequency synthesizer may be implemented within a single IC chip as a single mm-wave frontend IC chip or package.

First claim

What is claimed is:

1. A radio frequency (RF) frontend integrated circuit (IC) device, the RF frontend IC device comprising:
a first transceiver to transmit and receive RF signals associated with a first RF channel according to a first amplitude and phase shift setting within a predetermined frequency band;
a second transceiver to transmit and receive RF signals associated with a second RF channel according to a second amplitude and phase shift setting within the predetermined frequency band, wherein the second amplitude and phase shift setting is different from the first amplitude and phase shift setting; and
a frequency synthesizer coupled to the first transceiver and the second transceiver to perform frequency synchronization in a wide frequency spectrum, wherein the frequency synthesizer generates a local oscillator (LO) signal to the first transceiver and the second transceiver to enable the first transceiver and the second transceiver to transmit and receive the RF signals associated with the first RF channel and the second RF channel respectively, and
wherein the first transceiver, the second transceiver, and the frequency synthesizer are embedded within a single IC chip.

2. The RF frontend IC device of claim 1 , wherein the RF signals associated with the first RF channel are to be transmitted and received via a first antenna configured to radiate and receive according to the first amplitude and phase shift setting, and wherein the RF signals associated with the second RF channel are to be transmitted and received via a second antenna configured to radiate and receive according to the second amplitude and phase shift setting.

3. The RF frontend IC device of claim of claim 1 , wherein each of the first transceiver and the second transceiver comprises:
a transmitter to transmit a first RF signal to a first remote device;
a receiver to receive a second RF signal from a second remote device; and
a switch coupled to the transmitter and the receiver, wherein the switch is configured to couple the transmitter or the receiver to an antenna associated with the transceiver at a given point in time.

4. The RF frontend IC device of claim 3 , wherein the transmitter comprises:
a first intermediate frequency (IF) in-phase and quadrature (IQ) generator (IFIQ generator) to generate an IFIQ signal based on an IF signal received from a modem or a baseband processor;
a first LO IQ (LOIQ) generator to generate an LOIQ signal based on the LO signal received from the frequency synthesizer; and
a first mixer coupled to the first IFIQ generator and the first LOIQ generator to generate the first RF signal based on the IFIQ signal and the LOIQ signal.

5. The RF frontend IC device of claim 4 , wherein each of the first and second transceivers further comprises:
a first IF amplifier coupled to the first IFIQ generator and the first mixer, wherein the first IF amplifier is configured to amplify the IFIQ signal and to provide the amplified IFIQ signal to the first mixer; and
a first broadband amplifier coupled to the first mixer to amplify the first RF signal received from the first mixer.

6. The RF frontend IC device of claim 5 , wherein the first IF amplifier comprises:
a second IF amplifier to receive and amplify an in-phase IF signal derived from the IFIQ signal, wherein the in-phase IF signal is mixed with an in-phase LO signal derived from the LOIQ signal; and
a third IF amplifier to receive and amplify a quadrature IF signal derived from the IFIQ signal, wherein the quadrature IF signal is mixed with a quadrature LO signal derived from the LOIQ signal.

7. The RF frontend IC device of claim 3 , wherein the receiver comprises:
a second broadband amplifier configured to receive the second RF signal;
a second LOIQ generator to generate an LOIQ signal based on the LO signal received from the frequency synthesizer; and
a second mixer coupled to the second broadband amplifier and the second LOIQ generator, wherein the second mixer is configured to generate an IFIQ signal based on the amplified second RF signal and the LOIQ signal.

8. The RF frontend IC device of claim 7 , wherein the receiver further comprises:
a fourth IF amplifier coupled to the second mixer to receive and amplify the IFIQ signal from the second mixer; and
an IFIQ combiner coupled to the fourth IF amplifier to generate a combined IF signal based on the IFIQ signal.

9. The RF frontend IC device of claim 8 , wherein the fourth IF amplifier comprises:
a fifth IF amplifier to receive and amplify an in-phase IF signal derived from the IFIQ signal; and
a sixth IF amplifier to receive and amplify a quadrature IF signal derived from the IFIQ signal, wherein the IFIQ combiner is configured to combine the in-phase IF signal and the quadrature IF signal to generate the combined IF signal.

10. The RF frontend IC device of claim 1 , wherein the frequency synthesizer comprises:
a phase lock loop (PLL) circuitry to generate the LO signal associated with the predetermined frequency band based on a clock reference signal; and
an LO buffering device coupled to the PLL circuitry to buffer and to provide a first LO signal and a second LO signal derived from the LO signal to the first transceiver and the second transceiver respectively.

11. A radio frequency (RF) frontend integrated circuit (IC) device, the RF frontend IC device comprising:
an array of transceivers, each of the transceivers corresponding to one of a plurality of RF channels, wherein each of the RF channels includes a phase shifter configured to transmit and receive RF signals according to a respective phase shift setting within a predetermined frequency band, including shifting or compensating a phase of the RF signals according to the respective phase shift setting;
a frequency synthesizer coupled to each of the transceivers to perform frequency synchronization in a wide frequency spectrum, wherein the frequency synthesizer generates a local oscillator (LO) signal for each of the transceivers to enable each of the transceivers to transmit and receive the RF signals within its respective RF channel;
an up-converter coupled to each of the transceivers and the frequency synthesizer, wherein the up-converter is configured to up-convert a first intermediate frequency (IF) signal based on a LO signal into a first RF signal to be transmitted by the transceivers; and
a down-converter coupled to each of the transceivers and the frequency synthesizer, wherein the down-converter is configured to down-convert a second RF signal received from the transceivers based on the LO signal into a second IF signal,
wherein the array of transceivers, the frequency synthesizer, the up-converter, and the down-converter are embedded within a single IC chip.

12. The RF frontend IC device of claim 11 , wherein the up-converter comprises:
an IF in-phase and quadrature (IQ) generator (IFIQ generator) to generate an IFIQ signal based on the first IF signal;
an LOIQ generator to receive the LO signal from the frequency synthesizer to generate an LOIQ signal based on the LO signal; and
an up-convert mixer coupled to the IFIQ generator and the LOIQ generator, wherein the up-convert mixer is configured to generate the first RF signal based on the IFIQ signal and the LOIQ signal.

13. The RF frontend IC device of claim 12 , wherein the up-converter further comprises:
an IF amplifier coupled between the IFIQ generator and the up-convert mixer to amplify the first IF signal; and
a power divider coupled to the up-convert mixer to divide the first RF signal into a plurality of first RF sub-signals, wherein each first RF sub-signal is provided to one of the tran

Assignees

• Speedlink Tech Inc
• Speedlink Tech Inc
• Georgia Tech Res Inst

Inventors

• Chi Taiyun
• Wang Hua
• Chen Thomas

Classifications

• H03F3/195 Primary

  in integrated circuits · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title

• H04B1/44

  Transmit/receive switching · CPC title

• H04W72/0453

  Resources in frequency domain, e.g. a carrier in FDMA · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title