System, method, and apparatus for reducing power dissipation of sensor data on bit-serial communication interfaces

Patent metadata

Field	Value
Publication number	US-10135471-B2
Application number	US-201715612485-A
Country	US
Kind code	B2
Filing date	Jun 2, 2017
Priority date	Jun 2, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A communication system receives a binary sequence from a sensor, identifies a power consuming characteristic of the binary sequence, and determines an error component configured to reduce the power consuming characteristic of the binary sequence. The system compares the error component to an error tolerance deviation, and if the error component is below the error tolerance deviation, combines the error component with the binary sequence to produce an output sequence and transmits the output sequence via a serial interface to a receiver configured to receive the output sequence. The error threshold is based in part on an error tolerance characteristic of the receiver.

First claim

What is claimed is:

1. A method for reducing power in a data transmitting device, comprising the steps of:
receiving a binary sequence by the data transmitting device;
identifying a power consuming characteristic of the binary sequence;
determining an error component configured to reduce the power consuming characteristic of the binary sequence;
combining the error component with the binary sequence to produce an output sequence;
transmitting the output sequence via a serial interface; and
further comprising a first phase comprising the steps of:
checking each bit in a word of the binary sequence beginning from the least significant bit (LSB) to the most significant bit (MSB);
detecting a bit transition in the word; and
for each bit transition:
incrementing a stored number of bit transitions;
storing an index indicating the location of the bit transition;
storing a length of a run of 0s or 1s leading to the bit transition;
negating the run of 0s or 1s; and
accumulating a deviation in value resulting from negating the run.

2. The method of claim 1 , further comprising a second phase comprising the step of beginning from the MSB of the word and proceeding to the LSB, at each stored index removing the negating if the value deviation incurred by negating the run is offset by the runs of lower order bits of opposite polarity.

3. A communication system comprising:
a transmitter comprising a processor and a memory configured to store non-transitory instruction that when executed by the processor perform the steps comprising:
receiving a binary sequence;
identifying a power consuming characteristic of the binary sequence;
determining an error component configured to reduce the power consuming characteristic of the binary sequence;
comparing the error component to an error tolerance deviation;
if the error component is below the error tolerance deviation, combining the error component with the binary sequence to produce an output sequence; and
transmitting the output sequence via a serial interface; and

a receiver configured to receive the output sequence,
wherein the error threshold of the transmitting device is based in part on an error tolerance characteristic of the receiving device,
wherein the processor is further configured to perform the steps of:
a first phase comprising the steps of:
checking each bit in a word of the binary sequence beginning from the least significant bit (LSB) to the most significant bit (MSB);
detecting a bit transition in the word;
for each bit transition:
incrementing a stored number of bit transitions;
storing an index indicating the location of the bit transition;
storing a length of a run of 0s or 1s leading to the bit transition;
negating the run of 0s or 1s; and
accumulating a deviation in value resulting from negating the run; and

a second phase comprising the step of:
beginning from the MSB of the word and proceeding to the LSB, at each stored index removing the negating if the value deviation incurred by negating the run is offset by the runs of lower order bits of opposite polarity.

4. A serial communication interface device comprising:
a memory and a processor configured to execute non-transitory instruction stored in the memory to receive a binary sequence and produce an output sequence configured to reduce a power consuming characteristic of the binary sequence; and
a serial interface configured to transmit the output sequence,
wherein the processor is further configured to perform the steps of:
a first phase comprising the steps of:
checking each bit in a word of the binary sequence beginning from the least significant bit (LSB) to the most significant bit (MSB);
detecting a bit transition in the word;
for each bit transition:
incrementing a stored number of bit transitions;
storing an index indicating the location of the bit transition;
storing a length of a run of 0s or 1s leading to the bit transition;
negating the run of 0s or 1s; and
accumulating a deviation in value resulting from negating the run; and

a second phase comprising the step of:
beginning from the MSB of the word and proceeding to the LSB, at each stored index removing the negating if the value deviation incurred by negating the run is offset by the runs of lower order bits of opposite polarity.

Assignees

• Massachusetts Inst Technology

Inventors

• Stanley-Marbell Phillip
• Rinard Martin C

Classifications

• H04N19/156

  Availability of hardware or computational resources, e.g. encoding based on power-saving criteria · CPC title

• H04L1/0042

  Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence) · CPC title

• H03M7/14 Primary

  Conversion to or from non-weighted codes · CPC title

• H03M7/00

  Conversion of a code where information is represented by a given sequence or number of digits to a code where the same {, similar or subset of} information is represented by a different sequence or number of digits · CPC title

• H04B1/02 Primary

  Transmitters · CPC title