Load responsive jitter

Patent metadata

Field	Value
Publication number	US-10135343-B2
Application number	US-201815974264-A
Country	US
Kind code	B2
Filing date	May 8, 2018
Priority date	Apr 10, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A controller for use in a power converter that includes a current limit generator coupled to receive a feedback signal representative of an output of the power converter and generate an initial current limit signal. The controller includes a modulation circuit coupled to output a modulation signal which is a percentage of the initial current limit signal. An arithmetic operator is coupled to receive the initial current limit and selectively receive the modulation signal and output a current limit. A comparator is coupled to receive a current sense signal representative of a switch current conducted by a primary switch. A drive circuit is coupled to generate a drive signal to control switching of the primary switch to regulate the output of the power converter in response to the comparator output signal, and the drive circuit turns off the primary switch when the switch current has reached the current limit.

First claim

What is claimed is:

1. A controller for use in a power converter; the controller comprising:
a current limit generator coupled to receive a feedback signal representative of n output of the power converter and generate an initial current limit signal;
a modulation circuit coupled to output a modulation signal, wherein an amplitude swing of the modulation signal is a percentage of the initial current limit signal;
an arithmetic operator coupled to receive the initial current limit and selectively receive the modulation signal and output a current limit;
a comparator coupled to receive a current sense signal representative of a switch current conducted by a primary switch, wherein the comparator outputs a comparator output signal representative of whether the switch current has reached the current limit; and
a drive circuit coupled to generate a drive signal to control switching of the primary switch to regulate the output of the power converter in response to the comparator output signal, wherein the drive circuit turns off the primary switch when the switch current has reached the current limit.

2. The controller of claim 1 , wherein the controller further comprises a light load sense circuitry coupled to receive the initial current limit signal to sense a light load condition of the power converter and output a light load signal.

3. The controller of claim 2 , wherein the controller further comprises a secondary switch that conducts in response to the light load signal.

4. The controller of claim 2 , wherein the current limit is substantially the initial current limit when the light load condition is not sensed and wherein the current limit is substantially the current limit modulated by the modulation signal when the light load condition is sensed.

5. The controller of claim 4 , wherein the current limit is modulated such that the switching frequency of the drive signal is outside of the audible noise range.

6. The controller of claim 2 , wherein the light load sense circuitry determines the light load condition of the power converter when the initial current limit is less than a threshold.

7. The controller of claim 6 , wherein the threshold is substantially equal to 50% of a maximum value of the initial current limit.

8. The controller of claim 1 , wherein the arithmetic operator is coupled to receive the modulation signal when a secondary switch is closed.

9. The controller of claim 1 , wherein a switching frequency of the drive signal is modulated when the current limit is modulated by the modulation signal.

10. The controller of claim 1 , wherein the initial current limit signal may be one of a plurality of discrete values.

11. The controller of claim 1 , wherein the modulation signal may be a triangular waveform or a sawtooth waveform.

12. The controller of claim 1 , wherein the arithmetic operator is coupled to perform any number of arithmetic functions including addition, subtraction, multiplication, or division to the modulation signal and the initial current limit signal to output the current limit.

13. The controller of claim 1 , wherein the arithmetic operator is a terminal.

14. The controller of claim 1 , wherein the modulation circuit further comprises:
a counter coupled to receive a clock signal and increment or decrement a count in response to the clock signal; and
a digital to analog converter coupled to receive the count and generate the modulation signal in response to the count.

15. The controller of claim 14 , wherein the digital to analog converter comprises:
a plurality of current sources coupled to a plurality of switches, wherein the count controls the plurality of switches, wherein the modulation signal is the sum of the plurality of the current sources that are closed by the plurality of switches.

16. The controller of claim 1 , wherein the controller further includes a jitter generator coupled to output a jitter signal, wherein the jitter generator may modulate a switching frequency of the primary switch.

17. The controller of claim 16 , wherein the jitter signal may be received by an arithmetic operator or an oscillator coupled to generate a dock signal.

18. The controller of claim 1 , wherein the percentage of the initial current limit is in the range between 5% and 40%.

19. A controller for a switch mode power converter that comprises a primary switch, the controller comprising:
a comparator to compare a current sense signal representing current conducted by the primary switch with a current limit and, in response to the comparison indicating that the current conducted by the primary switch exceeds the current limit, output a signal indicative thereof;
power switch drive circuitry responsive to the signal indicative of the current exceeding the current limit to switch the primary switch into an off-state;
light load sense circuitry coupled to sense a light load on the switch mode power converter and output a light load signal in response thereto by closing a secondary switch; and
current limit modulation circuitry to modulate the current limit in response to the light load signal indicating a light load on the switch mode power converter.

20. The controller of claim 19 , wherein the power switch drive circuitry is responsive to a feedback signal representative of an output of the switch mode power converter.

21. The controller of claim 20 , wherein the controller further comprises a current limit generator coupled to generate an initial current limit in response to the feedback signal.

22. The controller of claim 21 , wherein the controller further comprises an arithmetic operator coupled to receive the initial current limit, wherein the current limit is the initial current limit.

23. The controller of claim 22 , wherein the arithmetic operator is coupled to receive the modulation signal when the secondary switch is closed, wherein the current limit is a modulated current limit.

24. The controller of claim 23 , wherein the arithmetic operator adds the modulation signal to the initial current limit.

25. The controller of claim 19 , wherein the current limit modulation circuitry generates a modulation signal in response to a system clock from an oscillator.

26. The controller of claim 25 , wherein the modulation signal has an amplitude swing of a range between 5% and 40% of the initial current limit.

27. The controller of claim 25 , current limit modulation circuitry comprises:
a counter coupled to receive a clock signal and increment or decrement a count in response to the clock signal, wherein the modulation signal is responsive to the increment or decrement of the count.

28. The controller of claim 19 , wherein the controller further comprises a jitter generator coupled to output a jitter signal, wherein the jitter generator modulates a switching frequency of the primary switch.

Assignees

• Power Integrations Inc

Inventors

• Djenguerian Alex B
• Vaughan Peter
• Lund Leif

Classifications

• H02M3/33507

  with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence) · CPC title

• H02M3/28 Primary

  using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title