Method of manufacturing solar cell

Patent metadata

Field	Value
Publication number	US-10134940-B2
Application number	US-201313751349-A
Country	US
Kind code	B2
Filing date	Jan 28, 2013
Priority date	Jul 30, 2010
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A method of manufacturing a solar cell includes: forming a solar cell substrate having one main surface and the other main surface and having a p-type surface and an n-type surface which are exposed on one region and another region in the one main surface, respectively; forming seed layers in an electrically separated state on the p-type surface and the n-type surface, respectively; and forming a plated film on the seed layer on each of the p-type surface and the n-type surface by an electrolytic plating method.

First claim

The invention claimed is:

1. A method of manufacturing a solar cell, comprising:
forming an insulating layer, a p-type amorphous silicon and an n-type amorphous silicon on a crystal n-type silicon substrate, the p-type amorphous silicon provided on one region and the n-type amorphous silicon provided on another region of a back surface of the crystal n-type silicon substrate, wherein the insulating layer is provided on the n-type amorphous silicon in a region, and a part of the p-type amorphous silicon is provided on the insulating layer in the region such that:
in the region, the n-type silicon substrate, the n-type amorphous silicon, the insulating layer, and the p-type amorphous silicon are stacked in the given order in a thickness direction orthogonal to the back surface and are overlapped with each other in the region in the thickness direction; and
in a plan view, each of the p-type amorphous silicon and the n-type amorphous silicon comprises finger portions extending in a first direction, wherein the finger portions of the p-type amorphous silicon and the finger portions of the n-type amorphous silicon are alternatingly provided in a second direction orthogonal to the first direction such that the finger portions of the p-type amorphous silicon are interdigitated with the finger portions of the n-type amorphous silicon on the back surface;

forming a seed layer on the p-type amorphous silicon and the n-type amorphous silicon;
removing a portion of the seed layer above the insulating layer to separate the seed layer to form a seed layer on the p-type amorphous silicon and a seed layer on the n-type amorphous silicon, wherein the seed layer formed on the p-type amorphous silicon and the seed layer formed on the n-type amorphous silicon are divided and electrically separated above the insulating layer such that a width of the seed layer on each of the finger portions of the p-type amorphous silicon is different from a width of the seed layer on each of the finger portions of the n-type amorphous silicon in the second direction; and
forming a plated film on the seed layer formed on the p-type amorphous silicon and a plated film on the seed layer formed on the n-type amorphous silicon by electrolytic plating using a common power source to supply currents to the seed layers on the p-type amorphous silicon and the n-type amorphous silicon such that the plated film formed on each finger portion of one of the p-type amorphous silicon and the n-type amorphous silicon, which has a larger width in the second direction than the plated film formed on each of the finger portions of the other of the p-type amorphous silicon and the n-type amorphous silicon, has a smaller thickness in the thickness direction orthogonal to a plane of the back surface than the plated film formed on each of the finger portions of the other of the p-type amorphous silicon and the n-type amorphous silicon.

2. The method of manufacturing a solar cell, according to claim 1 , wherein
forming the seed layers in the electrically separated state on the p-type amorphous silicon and the n-type amorphous silicon, respectively, includes forming a continuous metal layer on the p-type amorphous silicon and on the n-type amorphous silicon and then electrically separating the metal layer.

3. The method of manufacturing a solar cell, according to claim 1 , wherein
a front surface of the substrate is a light-receiving surface.

4. The method of manufacturing a solar cell, according to claim 3 , wherein
the substrate has a passivation film on the front surface.

5. The method of manufacturing a solar cell according to claim 1 , wherein
forming the seed layers forms the seed layers such that the width of each of the finger portions of the p-type amorphous silicon, is greater, in the second direction, than the width of each of the finger portions of the n-type amorphous silicon.

6. The method of manufacturing a solar cell according to claim 1 , wherein
forming the seed layers forms the seed layers such that an area of the seed layer on one of the p-type amorphous silicon and the n-type amorphous silicon that forms a pn junction, is greater than an area of the seed layer on the other of the p-type amorphous silicon and the n-type amorphous silicon.

7. A method of manufacturing a solar cell, comprising:
forming an n-type amorphous silicon on one region in a back surface of a crystal n-type silicon substrate,
forming an insulating layer on the n-type amorphous silicon,
forming a p-type amorphous silicon on another region in the back surface of the crystal n-type silicon substrate and on the insulating layer such that, in a region where the insulation layer is provided, the n-type silicon substrate, the n-type amorphous silicon, the insulating layer, and the p-type amorphous silicon are stacked in the given order in a thickness direction orthogonal to the back surface and are overlapped with each other in the thickness direction and such that each of the p-type amorphous silicon and the n-type amorphous silicon comprises finger portions extending in a first direction, wherein the finger portions of the p-type amorphous silicon and the finger portions of the n-type amorphous silicon are alternatingly provided in a second direction orthogonal to the first direction such that the finger portions of the p-type amorphous silicon are interdigitated with the finger portions of the n-type amorphous silicon on the back surface;
forming a seed layer on the p-type amorphous silicon and the n-type amorphous silicon;
removing a portion of the seed layer above the insulating layer to separate the seed layer to form a seed layer on the p-type amorphous silicon and a seed layer on the n-type amorphous silicon, wherein the seed layer formed on the p-type amorphous silicon and the seed layer formed on the n-type amorphous silicon are divided and electrically separated above the insulating layer such that a width of the seed layer on each of the finger portions of the p-type amorphous silicon is different from a width of the seed layer on each of the finger portions of the n-type amorphous silicon in the second direction; and
forming a plated film on the seed layer formed on the p-type amorphous silicon and a plated film on the seed layer formed on the n-type amorphous silicon by electrolytic plating using a common power source to supply currents to the seed layers on the p-type amorphous silicon and the n-type amorphous silicon such that the plated film formed on each finger portion of one of the p-type amorphous silicon and the n-type amorphous silicon, which has a larger width in the second direction than the plated film formed on each of the finger portions of the other of the p-type amorphous silicon and the n-type amorphous silicon, has a smaller thickness in the thickness direction orthogonal to a plane of the back surface than the plated film formed on each of the finger portions of the other of the p-type amorphous silicon and the n-type amorphous silicon.

Assignees

• Sanyo Electric Co
• Panasonic Ip Man Co Ltd

Inventors

• Goto Ryo
• Ide Daisuke
• Morigami Mitsuaki
• Murakami Youhei

Classifications

• H01L31/18 Primary

  Electricity · mapped topic

• Y02P70/521

  Cross-Sectional Technologies · mapped topic

• H01L31/1804

  Electricity · mapped topic

• H01L31/0747

  Electricity · mapped topic

• H01L31/022441

  Electricity · mapped topic