Insulated gate bipolar device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10134886-B2
Application number	US-201715657842-A
Country	US
Kind code	B2
Filing date	Jul 24, 2017
Priority date	Mar 16, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.

First claim

We claim:

1. A method for forming a semiconductor device comprising:
providing a first substrate having a first major surface and a second major surface opposed to the first major surface, a first doped region of a first conductivity type extending from the first major surface into the first substrate, and a polycrystalline semiconductor layer adjacent to the first major surface;
providing a second substrate having a dielectric layer disposed proximate to an outer surface;
attaching the second substrate to the first substrate such that the dielectric layer adjoins the polycrystalline semiconductor layer;
forming insulated trench gate electrode structures extending inward from the second major surface of the first substrate;
removing the second substrate to expose at least a portion of the dielectric layer;
removing at least a portion of the dielectric layer to expose at least a portion of the polycrystalline semiconductor layer;
doping the polycrystalline semiconductor layer with a dopant of a second conductivity type; and
forming a first electrode layer electrically coupled to the polycrystalline semiconductor layer, wherein the polycrystalline semiconductor layer provides an emitter region for the semiconductor device.

2. The method of claim 1 , wherein attaching comprises bonding the dielectric layer to the polycrystalline semiconductor layer.

3. The method of claim 1 , wherein doping the polycrystalline semiconductor layer comprises:
ion implanting the dopant of the second conductivity type into the polycrystalline semiconductor layer; and
annealing the dopant.

4. The method of claim 3 , wherein:
ion implanting comprises using a plurality of ion implants; and
at least one ion implant forms a second conductivity type doped region within the first substrate adjacent to the first major surface.

5. The method of claim 1 , wherein forming the first doped region comprises diffusing dopant of the first conductivity type from the polycrystalline semiconductor layer into the first substrate.

6. The method of claim 1 further comprising planarizing the polycrystalline semiconductor layer before attaching the second substrate.

7. The method of claim 6 further comprising oxidizing the polycrystalline semiconductor layer before planarizing.

8. The method of claim 1 further comprising:
incorporating one or more of phosphorous, arsenic, antimony, protons, and helium into the first substrate through the first major surface.

9. The method of claim 1 , wherein providing the polycrystalline semiconductor layer comprises forming a polysilicon layer having a thickness in a range from approximately 1,000 Angstroms through 20,000 Angstroms.

10. The method of claim 1 , wherein providing the polycrystalline semiconductor layer occurs before forming the first doped region.

11. The method of claim 1 , wherein forming the insulated trench gate electrode structures comprises:
forming a second doped region of the second conductivity type extending from the second major surface of the first substrate into the first substrate;
forming the insulated trench gate electrode structures extending inward from the second major surface;
forming source regions of the first conductivity type adjacent to the insulated trench gate electrode structures and within the second doped region; and
forming a second electrode layer electrically coupled to the source regions.

12. The method of claim 1 , wherein removing the second substrate comprises:
grinding a first portion of the second substrate; and
etching a second portion of second substrate to expose at least a portion of the dielectric layer.

13. The method of claim 1 , wherein forming the first doped region comprises using a plurality of ion implants.

14. The method of claim 1 , wherein:
doping the polycrystalline semiconductor layer comprises:
doping a first portion of the polycrystalline semiconductor layer with the dopant having the second conductivity type, wherein the first portion provides the emitter region; and
doping a second portion of the polycrystalline semiconductor layer with a second dopant having the first conductivity type, wherein the second portion and the first portion are laterally adjacent to each other so that the first electrode layer physically contacts both the first portion and the second portion.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Kuruc Marian
• Vavro Juraj

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title