Semiconductor having isolated gate structure

Patent metadata

Field	Value
Publication number	US-10134858-B2
Application number	US-201715493154-A
Country	US
Kind code	B2
Filing date	Apr 21, 2017
Priority date	Apr 13, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a plurality of stacked structures located in a trench of a dielectric layer, wherein each of the stacked structures comprises a metal gate, a cap, a selective buffer layer, a gate dielectric layer having a high dielectric constant, a bottom barrier layer and a common substrate, wherein the selective buffer layer is disposed on the common substrate, the gate dielectric layer having the high dielectric constant is disposed on the selective buffer layer, the bottom barrier layer is disposed on the gate dielectric layer having the high dielectric constant, the metal gate is disposed on the bottom barrier layer, and the cap is disposed on the metal gate, wherein an isolation slot isolates and contacts adjacent stacked structures at end to end, wherein the metal gates are constituted by a same work function metal layer and a same main conductive layer, and the work function metal layer and the main conductive layer have a continuous cross-sectional profile cut off by the isolation slot; and
a first dielectric layer directly disposed on the caps, wherein the isolation slot is an extension part of the first dielectric layer, and the first dielectric layer and the isolation slot are one piece, wherein the isolation slot is of same material composition as the first dielectric layer, and the isolation slot directly contacts each layer of the metal gate, the selective buffer layer, the gate dielectric layer having the high dielectric constant, and the bottom barrier layer, respectively.

2. The semiconductor structure according to claim 1 , wherein the metal gates and the caps have different materials.

3. The semiconductor structure according to claim 1 , wherein the caps comprise self-aligned contact (SAC) caps.

4. The semiconductor structure according to claim 1 , wherein the metal gates are constituted by a same top barrier layer, and the top barrier layer is sandwiched by the work function metal layer and the main conductive layer.

5. The semiconductor structure according to claim 1 , wherein the gate dielectric layer having the high dielectric constant and the bottom barrier layer are disposed under the work function metal layer.

6. The semiconductor structure according to claim 5 , wherein the gate dielectric layer having the high dielectric constant and the bottom barrier layer are U-shaped cross-sectional profiles.

7. The semiconductor structure according to claim 1 , wherein the dielectric layer is disposed on a substrate, wherein the substrate has a plurality of fin structures, and each of the metal gates is disposed across each of the fin structures respectively.

Assignees

• United Microelectronics Corp

Inventors

• Gan Tian Choy
• Hsiao Chu-Yun
• Huang Chun-Che
• Hsu Chia-Fu

Classifications

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title