Three dimensional memory array with select device

Patent metadata

Field	Value
Publication number	US-10134810-B2
Application number	US-201715604871-A
Country	US
Kind code	B2
Filing date	May 25, 2017
Priority date	Jun 11, 2013
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.

First claim

What is claimed is:

1. A method of forming a three dimensional memory array, comprising:
forming a stack comprising a plurality of first conductive lines separated from one another by insulation material;
forming a via through the stack such that at least a portion of the via passes through each of the plurality of first conductive lines;
forming a recess in at least one of the plurality of first conductive lines adjacent the via;
forming a select device in the recess;
forming a storage element material within the via, wherein the select device includes an inner concentric conductor material in physical contact with the storage element material and an outer concentric non-metallic material in physical contact with at least two surfaces of the inner concentric conductor material; and
forming a conductive extension within the via.

2. The method of claim 1 , further comprising forming a buffer material in the via adjacent the storage element material and the conductive extension.

3. The method of claim 1 , wherein forming a select device in the recess includes:
Forming the non-metallic material in the recess; and
forming the conductor material in the recess.

4. The method of claim 3 , wherein forming the conductor material in the recess includes forming the conductor material of a same material as the plurality of first conductive lines.

5. The method of claim 3 , wherein forming a select device in the recess includes:
first forming the non-metallic material in the recess; and
subsequently forming the conductor material in the recess.

6. The method of claim 3 , wherein forming the non-metallic material in the recess includes:
depositing a semiconductor material in the recess; and
removing only a portion of the semiconductor material in the recess to form a second recess.

7. The method of claim 6 , wherein depositing the semiconductor material in the recess includes conformally depositing the semiconductor material in the via and recess by a chemical vapor deposition (CVD) method when the plurality of first conductive lines includes less than six (6) first conductive lines and the via has an aspect ratio of less than six-to-one (6:1).

8. The method of claim 6 , wherein depositing the semiconductor material in the recess includes conformally depositing the semiconductor material in the via and recess by an atomic layer deposition (ALD) method when the plurality of first conductive lines includes between fourteen (14) and nineteen (19) inclusive, and the via has an aspect ratio of between nine-to-one (9:1) and eleven-to-one (11:1).

9. The method of claim 6 , wherein forming the conductor material in the recess includes forming the conductor material in the second recess.

10. The method of claim 3 , wherein forming the recess includes forming the recess at an exposed region of each of the first conductive lines in a wall of the via by a non-directional etch that is more selective to the first conductive lines than the insulation material; and
wherein forming the conductor material in the recess includes:
depositing the conductor material within the recess, and
removing the conductor material not within the recess.

11. The method of claim 1 , further comprising forming a plurality of second conductive lines arranged to extend substantially perpendicular to the plurality of first conductive lines at a different level than a number of levels at which the plurality of first conductive lines are arranged, and arranged to extend substantially perpendicular to the conductive extension,
wherein the conductive extension is coupled to at least one of the plurality of second conductive lines.

12. The method of claim 11 , wherein forming the plurality of second conductive lines includes forming the plurality of second conductive lines by a dual-damascene process.

13. A method of forming a memory array, comprising:
forming a stack comprising a number of first conductive lines separated from one another by insulation material;
forming a via through the stack such that at least a portion of the via passes through each of the number of first conductive lines;
forming a recess in at least one of the number of first conductive lines adjacent the via;
forming a select device in the recess in the number of first conductive lines adjacent the via;
forming storage element material within the via adjacent the select device, wherein the select device includes an inner concentric conductor material in physical contact with the storage element material and an outer concentric non-metallic material in physical contact with at least two surfaces of the inner concentric conductor material; and
forming a conductive extension concentrically within the storage element material.

14. The method of claim 13 , wherein forming the select device in the recess includes forming one of a metal-semiconductor-metal device and a metal-insulator-metal device with one of the number of first conductive lines.

15. The method of claim 14 , wherein forming the via includes forming the via to have a particular aspect ratio, and forming the select device includes depositing material comprising the select device in the recess,
wherein the particular aspect ratio of the via and the process by which the material comprising the select device is deposited in the recess is based on a current density of the select device.

16. A method of forming a memory array, comprising:
forming a stack comprising a plurality of conductive lines separated from one another by insulation material;
forming at least one conductive extension such that the at least one conductive extension is arranged to extend substantially perpendicular to the plurality of conductive lines, wherein the at least one conductive extension intersects at least one conductive line among the plurality of conductive lines;
forming a storage element material around the at least one conductive extension;
forming a buffer material such that buffer material is disposed concentrically between and in physical contact with the at least one conductive extension and the storage element; and
forming a select device such that the select device is arranged around the storage element material, wherein the select device includes an inner concentric conductor material in physical contact with the storage element and an outer concentric non-metallic material in physical contact with at least two surfaces of the inner concentric conductor material.

17. The method of claim 16 , further comprising forming the select device such that select device includes an inner concentric conductor material in physical contact with the storage element material at two discrete locations, and an outer concentric non-metallic material arranged around the inner concentric conductor material such that the outer concentric non-metallic material is in physical contact with a first surface, a second surface, and a third surface of the inner concentric conductor material.

18. The method of claim 16 , further comprising forming the select device such that the select device includes a non-metallic material at an outside diameter of a ring geometry and a conductor material at an inside diameter of the ring geometry and in physical contact with the storage element material at two discrete locations.

19. The method of claim 16 , further comprising forming a second buffer material around the storage element material, the second buffer material being located between the select device and the storage element material.

20. The method of c

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy D V Nirmal
• Sills Scott E
• Sandhu Gurtej S

Classifications

• H01L45/06

  Electricity · mapped topic

• H01L27/249 Primary

  Electricity · mapped topic

• H01L27/2427

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L27/2409

  Electricity · mapped topic