Array substrate, method of producing array substrate, and display panel

Patent metadata

Field	Value
Publication number	US-10134771-B2
Application number	US-201615276221-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Jun 19, 2014
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

An array substrate, a method of producing the array substrate, and a display panel incorporating the array substrate are disclosed. The array substrate includes a substrate, a gate line, a data line, and a spacer. The gate line and the data line are arranged over the substrate. The spacer is arranged over the gate line and the data line. The gate line and/or the data line is provided with a via hole at a position corresponding to a spacer. In this manner, a problem of a display panel having gaps of different sizes after assembly because of non-uniform thicknesses of the gate line and/or the data line can be avoided, which, in turn, prevents inhomogeneous color in the display.

First claim

The invention claimed is:

1. An array substrate comprising:
a substrate;
a gate line and a data line arranged over the substrate;
a spacer arranged over the gate line and the data line; and
a via hole physically penetrating through at least one of the gate line and the data line, wherein an orthographic projection of the via hole on the substrate at least partially overlaps with an orthographic projection of the spacer on the substrate.

2. The array substrate according to claim 1 , further comprising:
a gate insulating layer between the gate line and the spacer;
wherein the gate insulating layer is provided with a second via hole, wherein an orthographic projection of the second via hole on the substrate at least partially overlaps with an orthographic projection of the spacer on the substrate.

3. The array substrate according claim 1 , further comprising:
a passivation layer between the data line and the spacer; and
a further via hole arranged in the passivation layer, wherein an orthographic projection of the further via hole on the substrate at least partially overlaps with the orthographic projection of the spacer on the substrate.

4. The array substrate according to claim 1 , further comprising:
a gate insulating layer;
an active layer;
a passivation layer; and
an ITO pixel electrode layer;
wherein each of the gate insulating layer, the active layer, the passivation layer; and the ITO pixel electrode layer are disposed between the gate line and the spacer.

5. The array substrate according to claim 1 , further comprising:
a passivation layer; and
an ITO pixel electrode layer;
wherein each of the passivation layer and the ITO pixel electrode layer are disposed between the date line and the spacer.

6. The array substrate according to claim 1 , further comprising:
a first ITO pixel electrode layer;
a gate insulating layer;
an active layer;
a passivation layer; and
a second ITO pixel electrode layer;
wherein each of the first ITO pixel electrode layer, the gate insulating layer, the active layer, the passivation layer; and the second ITO pixel electrode layer are disposed between the gate line and the spacer.

7. A method for producing an array substrate, comprising:
forming a gate line and a data line over a substrate;
forming a spacer over the gate line and the data line; and
forming a via hole physically penetrating through at least one of the rate line and the data line, wherein an orthographic projection of the via hole on the substrate at least partially overlaps with an orthographic projection of the spacer on the substrate.

8. The method according to claim 7 , wherein forming the gate line over the substrate comprises:
forming a gate metal layer over the substrate; and
patterning the gate metal layer to form a pattern of the gate line.

9. The method according to claim 7 , wherein forming, in the gate line, a via hole comprises:
forming a gate insulating layer on the gate line; and
forming a via hole penetrating the gate line and the gate insulating layer, wherein an orthographic projection of the via hole on the substrate at least partially overlaps with an orthographic projection of the spacer on the substrate.

10. The method according to claim 9 , wherein forming the data line over the substrate comprises:
forming a source/drain metal layer on the gate insulating layer; and
patterning the source/drain metal layer to form a pattern of the data line.

11. The method according to claim 7 , further comprising:
forming a passivation layer on the data line; and
forming a further via hole in the passivation layer, wherein an orthographic projection of the further via hole on the substrate at least partially overlaps with an orthographic projection of the spacer on the substrate.

12. A display panel, comprising:
an array substrate comprising:
a substrate;
a gate line and a data line arranged over the substrate; and
a spacer arranged over the gate line and the data line;
a via hole physically penetrating through at least one of the gate line and the data line, wherein an orthographic projection of the via hole on the substrate at least partially overlaps with an orthographic projection of the spacer on the substrate; and
an opposite substrate;
wherein the spacer is arranged between the array substrate and the opposite substrate so as to define the gap between the array substrate and the opposite substrate.

13. The display panel according to claim 12 , wherein the array substrate further comprises:
a gate insulating layer between the gate line and the spacer;
wherein the gate insulating layer is provided with a second via hole, wherein an orthographic projection of the second via hole on the substrate at least partially overlaps with an orthographic projection of the spacer on the substrate.

14. The display panel according to claim 12 , wherein the array substrate further comprises:
a passivation layer between the data line and the spacer;
wherein the passivation layer is provided with a further via hole, wherein an orthographic projection of the further via hole on the substrate at least overlaps with an orthographic projection of the spacer on the substrate.

15. The display panel according to claim 12 , wherein the array substrate further comprises:
a gate insulating layer;
an active layer;
a passivation layer; and
an ITO pixel electrode layer;
wherein each of the gate insulating layer, the active layer, the passivation layer; and the ITO pixel electrode layer are disposed between the gate line and the spacer.

16. The display panel according to claim 12 , wherein the array substrate further comprises:
a passivation layer; and
an ITO pixel electrode layer;
wherein each of the passivation layer and the ITO pixel electrode layer are disposed between the date line and the spacer.

17. The display panel according to claim 12 , wherein the array substrate further comprises:
a first ITO pixel electrode layer;
a gate insulating layer;
an active layer;
a passivation layer; and
a second ITO pixel electrode layer;
wherein each of the first ITO pixel electrode layer, the gate insulating layer, the active layer, the passivation layer; and the second ITO pixel electrode layer are disposed between the gate line and the spacer.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co
• Beijing Boe Display Tech Group Co Ltd

Inventors

• Xi Yusheng
• Hu Haichen
• Tian Ming

Classifications

• H01L27/124 Primary

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• H01L27/1248

  Electricity · mapped topic

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title