Oxide semiconductor TFT array substrate and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10134765-B2
Application number	US-201615170433-A
Country	US
Kind code	B2
Filing date	Jun 1, 2016
Priority date	Jun 3, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A method for manufacturing an oxide semiconductor TFT array substrate is provided, which including: successively depositing an oxide semiconductor active layer and a transparent conductive layer on a base substrate without breaking vacuum; and forming patterns of an active layer and a transparent conductive layer. An oxide semiconductor TFT array substrate is further provided.

First claim

What is claimed is:

1. A method for manufacturing an oxide semiconductor array substrate, comprising:
successively depositing an oxide semiconductor material layer and a transparent conductive material layer on a base substrate without breaking vacuum;
forming a source/drain metal layer on the transparent conductive material layer; and
forming patterns of source/drain electrodes, a transparent conductive layer, and an oxide semiconductor active layer through one patterning process, wherein forming patterns of source/drain electrodes, the transparent conductive layer, and the oxide semiconductor active layer through one patterning process comprises:
forming a photoresist layer on the source/drain metal layer;
exposing the photoresist layer through a half-tone mask and developing;
removing portions of the source/drain metal layer other than a portion of the source/drain metal layer configured to form the source/drain electrodes and a portion of the source/drain metal layer within in an effective display area of a pixel unit,
performing a first ashing process on retained photoresist layer after developing, so as to expose a region of the source/drain metal layer in a channel region to be formed;
etching the exposed region of the source/drain metal layer in the channel region to be formed so as to form the channel region;
partially etching a portion of the transparent conductive material layer within the channel region in a direction along a thickness of the transparent conductive material layer;
performing a second ashing process on the retained photoresist layer so as to expose a portion of the transparent conductive material layer other than a portion of the transparent conductive material layer for a drain electrode connected with a data line;
removing the portion of the transparent conductive material layer other than the portion of the transparent conductive material layer for the drain electrode connected with the data line; and
removing a portion of the transparent conductive material layer retained in the channel region.

2. The method according to claim 1 , wherein before successively depositing the oxide semiconductor material layer and the transparent conductive material layer on the base substrate without breaking vacuum, the method further comprising:
forming a gate metal layer; and
forming a pattern of a gate electrode by one other patterning process.

3. The method according to claim 1 , wherein after forming patterns of an oxide semiconductor active layer and a transparent conductive layer through one patterning process, the method further comprises:
forming a gate metal layer, and forming a pattern of gate electrode through one patterning process.

4. The oxide semiconductor array substrate according to claim 1 , wherein the oxide semiconductor active layer has a reduced thickness in a channel region of the thin film transistor.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Yin Bingkun
• Han Junhao

Classifications

• H10P14/3426

  Oxides · CPC title

• H01L21/02554

  Electricity · mapped topic

• H01L29/66765

  Electricity · mapped topic

• H01L29/78678

  Electricity · mapped topic

• H01L29/78669

  Electricity · mapped topic