Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10134744-B1
Application number	US-201715681444-A
Country	US
Kind code	B1
Filing date	Aug 21, 2017
Priority date	Aug 21, 2017
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL 2 ) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first inverter, comprising a first pull-up transistor and a first pull-down transistor;
a second inverter, comprising a second pull-up transistor and a second pull-down transistor, wherein the first inverter and the second inverter forms a latch circuit;
a first inner access transistor and a first outer access transistor, electrically connected to the latch circuit and a first word line; and
a second inner access transistor and a second outer access transistor, electrically connected to the latch circuit and a second word line, wherein the second inner access transistor comprises a first channel width which is different from a second channel width of the second outer access transistor, wherein the second inner access transistor comprises a gate across a first active area, the second outer access transistor comprises the gate across a second active area, and a width of the second active area is relative greater than a width of the first active area in a first direction.

2. The layout of a semiconductor memory device of claim 1 , wherein the first active area and the second active are both disposed on a planar substrate.

3. The layout of a semiconductor memory device of claim 1 , wherein the first active area is disposed on a planar substrate and the second active area is disposed on a plurality of fins.

4. The layout of a semiconductor memory device of claim 1 , wherein the first active area and the second active area are both disposed on a plurality of fins, and the second active area includes more number of fins than that of the first active area.

5. The layout of a semiconductor memory device of claim 1 , wherein a resistance of the second inner access transistor is greater than a resistance of the second outer access transistor.

6. The layout of a semiconductor memory device of claim 1 , wherein a doped concentration of the first active area is different than a doped concentration of the second active area.

7. The layout of a semiconductor memory device of claim 6 , wherein the doped concentration of the second active area is greater than the doped concentration of the first active area.

8. The layout of a semiconductor memory device of claim 1 , wherein dopants implanted in the first active area and the second active area are different.

9. The layout of a semiconductor memory device of claim 1 , further comprising:
a plurality of plugs electrically connected to the first active area and the second active area respectively, wherein a number of the plugs electrically connected to the second active area is greater than a number of the plugs electrically connected to the first active area.

10. The layout of a semiconductor memory device of claim 1 , further comprising:
a silicide layer disposed on the second active area.

11. The layout of a semiconductor memory device of claim 1 , wherein the first inner access transistor and the first outer access transistor respectively connected to a first bit line and a second bit line.

12. The layout of a semiconductor memory device of claim 1 , wherein the second inner access transistor and the second outer access transistor respectively connected to a third bit line and a fourth bit line.

13. The layout of a semiconductor memory device of claim 1 , wherein the first inner access transistor comprises another gate across a third active area, the first outer access transistor comprises the another gate across a fourth active area, and the another gate and the gate are both extended along the first direction.

14. The layout of a semiconductor memory device of claim 13 , wherein a width of the third active area is different from a width of the fourth active area in the first direction.

15. The layout of a semiconductor memory device of claim 13 , wherein a width of the fourth active area is greater than a width of the third active area.

16. The layout of a semiconductor memory device of claim 1 , wherein a resistance of the first inner access transistor is greater than a resistance of the first outer access transistor.

17. The layout of a semiconductor memory device of claim 13 , wherein a doped concentration of the fourth active area is greater than a doped concentration of the third active area.

18. The layout of a semiconductor memory device of claim 13 , wherein dopants implanted in the third active area and the fourth active area are different.

Assignees

• United Microelectronics Corp

Inventors

• Chen Chih-Han
• Chen Wei-Chi
• Chang Ching
• Chen Ming-Shing
• Wu Chao-Hsien
• Hwang Chia-Hui
• Huang Lu-Ran

Classifications

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G11C11/404

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/417 Primary

  for memory cells of the field-effect type · CPC title

• G11C7/1075

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title