Polycrystalline ceramic substrate and method of manufacture

US10134589B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10134589-B2
Application numberUS-201715621235-A
CountryUS
Kind codeB2
Filing dateJun 13, 2017
Priority dateJun 24, 2016
Publication dateNov 20, 2018
Grant dateNov 20, 2018

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating a substantially planar ceramic substrate structure, the method comprising: providing a ceramic substrate having a front surface characterized by a plurality of naturally occurring voids, the ceramic substrate comprising a polycrystalline material; encapsulating the ceramic substrate in a barrier layer; forming a bonding layer comprising a bonding layer material and coupled to the barrier layer on the front surface of the ceramic substrate; removing a portion of the bonding layer to expose at least a portion of the barrier layer and to define fill regions filled with the bonding layer material in spaces of the plurality of naturally occurring voids; and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions. 2. The method of claim 1 wherein the ceramic substrate comprises polycrystalline aluminum nitride. 3. The method of claim 1 wherein removing the portion of the bonding layer comprises a chemical-mechanical polishing (CMP) process. 4. The method of claim 3 wherein the CMP process terminates at the barrier layer. 5. The method of claim 4 wherein the barrier layer comprises silicon nitride. 6. The method of claim 1 wherein the front surface of the ceramic substrate is characterized by an RMS roughness in the range of 50-600 nm and the second bonding layer is characterized by an RMS roughness in the range of 0.5-5 nm. 7. The method of claim 1 wherein the bonding layer comprises silicon oxide and the second bonding layer comprises a silicon oxide layer between 100 nm and 1,000 nm in thickness. 8. The method of claim 1 wherein the second bonding layer comprises a different material than the bonding layer. 9. The method of claim 8 wherein the bonding layer comprises silicon oxide and the second bonding layer comprises DLC. 10. The method of claim 1 further comprising, after removing a portion of the bonding layer, forming a second barrier shell encapsulating the exposed barrier layer and the fill regions. 11. The method of claim 1 wherein forming the bonding layer comprises repeating a cycle of deposition/polishing one or more times. 12. The method of claim 11 wherein the repeated cycle of deposition/polishing comprises deposition of different materials. 13. The method of claim 1 further comprising: joining a substantially single crystal layer to the second bonding layer, wherein the substantially single crystal layer is characterized by a first surface roughness; processing the substantially single crystal layer to form a growth surface characterized by a second surface roughness less than the first surface roughness; and forming an epitaxial layer coupled to the growth surface. 14. A method of fabricating a substantially planar ceramic substrate structure, the method comprising: providing a ceramic substrate having a front surface characterized by a plurality of naturally occurring peaks, the ceramic substrate comprising a polycrystalline material; forming a bonding layer comprising a bonding layer material and coupled to the front surface of the ceramic substrate; performing a chemical-mechanical polishing (CMP) process to remove a portion of the bonding layer to expose at least a portion of the front surface of the ceramic substrate and to define fill regions filled with the bonding layer material between adjacent peaks of the plurality of naturally occurring peaks on the front surface of the ceramic substrate; and encapsulating the ceramic substrate in a barrier layer. 15. The method of claim 14 further comprising depositing an adhesion promotion layer between the front surface of the ceramic substrate and the bonding layer. 16. The method of claim 14 wherein, the ceramic substrate comprises polycrystalline aluminum nitride. 17. The method of claim 14 further comprising depositing an electrically conductive layer coupled to at least a portion of the barrier layer. 18. The method of claim 14 further comprising depositing a thermally conductive layer coupled to at least a portion of the barrier layer. 19. The method of claim 14 further comprising depositing a second bonding layer coupled to at least a portion of the barrier layer. 20. The method of claim 14 further comprising: depositing an electrically conductive layer coupled to at least a portion of the barrier layer; depositing a thermally conductive layer coupled to at least a portion of the electrically conductive layer; and depositing a second bonding layer coupled to at least a portion of the thermally conductive layer.

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What does patent US10134589B2 cover?
A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the a…
Who is the assignee on this patent?
Qromis Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/2921. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 20 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).