Computer architecture to provide flexibility and/or scalability

Patent metadata

Field	Value
Publication number	US-10133697-B2
Application number	US-201715678188-A
Country	US
Kind code	B2
Filing date	Aug 16, 2017
Priority date	Dec 26, 2013
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1U) implementation, a four rack unit (4U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.

First claim

We claim:

1. A rack-scale architecture comprising:
a first module slot to accommodate a first hardware module; and
a peripheral component interconnect express (PCIe) fabric between the first module slot and a fabric interface that is to accommodate a network fabric, wherein the PCIe fabric is to include:
a first PCIe link to couple the first module slot with the fabric interface to provide a communication path between the first hardware module and the network fabric; and
a second PCIe link to couple the first module slot with a second module slot that is to accommodate a second hardware module to provide a communication path between the first hardware module and the second hardware module that excludes the network fabric, wherein the first hardware module and the second hardware module are to be physically removable and replaceable hardware modules, and wherein one or more of the first hardware module or the second hardware module includes a processor module and the network fabric is to be populated at the fabric interface, wherein one of the first hardware module or the second hardware module includes a processor module, the other of the first hardware module or the second hardware module includes a memory module, and the network fabric is to be depopulated at the fabric interface, or wherein one of the first hardware module or the second hardware module includes a processor module, the other of the first hardware module or the second hardware module includes a security module, and the network fabric is to be depopulated at the fabric interface.

2. The architecture of claim 1 , further including a third PCIe link to couple the second module slot with the fabric interface to provide a communication path between the second hardware module and the network fabric.

3. The architecture of claim 1 , wherein the network fabric is to be utilized when hardware modules communicate across respective PCIe links located between respective module slots and the fabric interface.

4. The architecture of claim 2 , wherein the hardware modules are processor modules.

5. The architecture of claim 1 , wherein the network fabric is to be bypassed when hardware modules communicate across one or more PCIe links coupling respective module slots with each other.

6. The architecture of claim 5 , wherein the network fabric is to be bypassed when a processor module and an I/O module communicate across one PCIe link coupling respective slots with each other.

7. The architecture of claim 5 , wherein the network fabric is to be bypassed when processor modules communicate across respective PCIe links located between respective module slots and a bridge external to the network fabric.

8. The architecture of claim 1 , wherein the network fabric is to be bypassed when hardware modules communicate across a dual star PCIe link.

9. The architecture of claim 1 , further including an on-backboard Ethernet switch to exclude a top-of-rack switch.

10. The architecture of claim 1 , further including a fixed function backboard coupled with one or more of the first module slot or the second module slot, wherein the fixed function backboard is to accommodate one or more of a pre-installed I/O element or a pre-installed management element.

11. The architecture of claim 1 , further including a dynamic function backboard coupled with one or more of the first module slot or the second module slot, wherein the dynamic function backboard is to accommodate one or more of a user-installed I/O element or a user-installed management element.

12. The architecture of claim 11 , wherein the user-installed I/O element includes one or more of a chipset or a storage device, and wherein the user-installed management element includes one or more of a thermal management element, a power management element, or a controller.

13. A method comprising:
providing a first module slot to accommodate a first hardware module; and
providing a peripheral component interconnect express (PCIe) fabric between the first module slot and a fabric interface that is to accommodate a network fabric, wherein the PCIe fabric includes:
a first PCIe link to couple the first module slot with the fabric interface to provide a communication path between the first hardware module and the network fabric; and
a second PCIe link to couple the first module slot with a second module slot that is to accommodate a second hardware module to provide a communication path between the first hardware module and the second hardware module that excludes the network fabric, wherein the first hardware module and the second hardware module are to be physically removable and replaceable hardware modules, and wherein one or more of the first hardware module or the second hardware module includes a processor module and the network fabric is to be populated at the fabric interface, wherein one of the first hardware module or the second hardware module includes a processor module, the other of the first hardware module or the second hardware module includes a memory module, and the network fabric is to be depopulated at the fabric interface, or wherein one of the first hardware module or the second hardware module includes a processor module, the other of the first hardware module or the second hardware module includes a security module, and the network fabric is to be depopulated at the fabric interface.

14. The method of claim 13 , further including providing a third PCIe link to couple the second module slot with the fabric interface to provide a communication path between the second hardware module and the network fabric.

15. The method of claim 13 , wherein the network fabric is utilized when hardware modules communicate across respective PCIe links located between respective module slots and the fabric interface, wherein the network fabric is bypassed when hardware modules communicate across one or more PCIe links coupling respective module slots with each other, or wherein the network fabric is bypassed when hardware modules communicate across a dual star PCIe link.

16. The method of claim 13 , further including providing an on-backboard Ethernet switch to exclude a top-of-rack switch.

17. The method of claim 13 , further including one or more of:
providing a fixed function backboard coupled with one or more of the first module slot or the second module slot, wherein the fixed function backboard is to accommodate one or more of a pre-installed I/O element or a pre-installed management element; or
providing a dynamic function backboard coupled with one or more of the first module slot or the second module slot, wherein the dynamic function backboard is to accommodate one or more of a user-installed I/O element or a user-installed management element.

Assignees

• Intel Corp

Inventors

• Blevins Dirk F
• Morgan John M
• Goldschmidt Marc A
• Pullin Edward J

Classifications

• G06F13/20

  for access to input/output bus · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title