Coordinating memory operations using memory-device generated reference signals

Patent metadata

Field	Value
Publication number	US-10133693-B2
Application number	US-201715827825-A
Country	US
Kind code	B2
Filing date	Nov 30, 2017
Priority date	Feb 23, 2010
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

First claim

What is claimed is:

1. A memory controller comprising:
controller logic; and
a physical interface communicatively coupled to the controller logic and operable to receive a shared reference signal from a memory device, the shared reference signal varying with an operating temperature of the memory device, and to time communication of data with the memory device to the shared reference signal.

2. The memory controller of claim 1 , the physical interface including a clock synthesis circuit to generate, responsive to the shared reference signal, an internal clock signal that varies with the operating temperature of the memory device, the communication of data timed to the internal clock signal.

3. The memory controller of claim 2 , wherein the communication of the data includes writing data to the memory device timed to the internal clock signal.

4. The memory controller of claim 1 , further comprising:
a second physical interface communicatively coupled to the controller logic and operable to receive a second shared reference signal from a second memory device, the second shared reference signal varying with a second operating temperature of the second memory device, the second physical interface to time communication of second data with the second memory device to the second shared reference signal.

5. The memory controller of claim 4 , wherein the first-mentioned operating temperature differs from the second operating temperature.

6. The memory controller of claim 1 , for use with at least two memory devices each of which transmits an associated shared reference signal to the memory controller for the memory controller to time communication with the associated memory device, wherein the memory controller has at least two controller physical interfaces each dedicated to a respective one of the at least two memory devices.

7. The memory controller of claim 6 , further comprising a clock alignment circuit for each one of the at least two controller physical interfaces to adjust each of a transmit phase and a receive phase associated with at least one controller operation for the associated memory device.

8. The memory controller of claim 7 , wherein the clock alignment circuit for each one of the at least two controller interfaces is operable to coordinate the at least one controller operation according to a unique frequency for each memory device, the unique frequency established by the associated shared reference signal.

9. A memory system comprising:
controller logic; and
a physical interface communicatively coupled to the controller logic and operable to receive a shared reference signal from a memory device, the shared reference signal varying with an operating temperature of the memory device, and to time communication of data with the memory device to the shared reference signal.

10. The memory system of claim 9 , further comprising the memory device and a bus extending between the physical interface and the memory device to communicate the shared reference signal from the memory device to the memory controller.

11. The memory system of claim 10 , further comprising:
a second memory device;
a second physical interface coupled to the controller logic and operable to receive a second shared reference signal from the second memory device; and
a second bus extending between the second physical interface and the second memory device to communicate the second shared reference signal from the second memory device to the second physical interface.

12. The memory system of claim 11 , further comprising:
a first clock synthesis circuit to generate, responsive to the first-mentioned shared reference signal, a first clock signal that varies with the operating temperature of the first-mentioned memory device; and
a second clock synthesis circuit to generate, responsive to the second shared reference signal, a second clock signal that varies with the operating temperature of the second memory device.

13. The memory system of claim 10 , wherein the memory device includes integrated physical structures that oscillate at a frequency that varies with the operating temperature.

14. The memory system of claim 13 , the integrated physical structures forming a tank circuit.

15. A method for synchronizing a memory system, the method comprising:
developing, on a memory device, a shared reference signal of a frequency that varies with of an operating temperature of the memory device;
receiving, on a memory controller, the shared reference signal of the frequency that varies with the operating temperature of the memory device; and
timing a write operation to the shared reference signal, the write operation to write data from the memory controller to the memory device.

16. The method of claim 15 , further comprising:
developing, on a second memory device, a second shared reference signal of a frequency that varies with of an operating temperature of the second memory device;
receiving, on the memory controller, the second shared reference signal of the frequency that varies with the operating temperature of the second memory device; and
timing a second write operation to the second shared reference signal, the second write operation to write data from the memory controller to the second memory device.

17. The method of claim 16 , wherein the operating temperature of the first-mentioned memory device differs from the operating temperature of the second memory device.

18. The method of claim 15 , further comprising deriving a clock signal from the shared reference signal and timing the write operation to the clock signal.

19. The method of claim 15 , wherein the memory device is an integrated circuit comprising physical structures that oscillate at the frequency.

20. The method of claim 19 , wherein the physical structures include an inductor.

Assignees

• Rambus Inc

Inventors

• Best Scott C
• Shaeffer Ian

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title