Synchronous input/output (I/O) cache line padding

Patent metadata

Field	Value
Publication number	US-10133691-B2
Application number	US-201615190262-A
Country	US
Kind code	B2
Filing date	Jun 23, 2016
Priority date	Jun 23, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.

First claim

What is claimed is:

1. A computer-implemented method for synchronous input/output (I/O) cache line padding between a server having a processor executing an operating system and a recipient control unit, the method comprising:
receiving, via the processor, at the recipient control unit, a partial cache line direct memory access (DMA) write request;
fetching, via the processor, a device table entry (DTE) associated with the partial cache line DMA write request;
determining, via the processor, a cache line size for a synchronous I/O cache line;
determining, via the processor, whether a cache line padding bit in the DTE is set;
based on determining that the cache line padding bit in the DTE is set, writing a full cache line DMA write request by padding, via the processor, the partial cache line DMA write request with a padded portion, wherein the padded portion is based on an echo read portion and the cache line size; and
based on determining that the cache line padding bit in the DTE is not set, writing the partial cache line DMA write request.

2. The computer-implemented method of claim 1 , wherein the full cache line DMA write request comprises the partial cache line DMA write request and the padded portion.

3. The computer-implemented method of claim 1 , wherein the full cache line DMA write request is the same size as an address length boundary size.

4. The computer-implemented method of claim 1 , wherein the cache line size of the server is configured for 256 bytes of information.

5. The computer-implemented method of claim 1 , wherein the full cache DMA write request comprises an 8 byte portion and the padded portion, wherein the padded portion is 248 bytes of information.

6. The computer-implemented method of claim 1 , wherein the padded portion consists of zeroes.

7. The computer-implemented method of claim 1 , wherein the server and the recipient control unit have different cache line sizes.

8. The computer-implemented method of claim 1 , wherein the echo read portion is a confirmation that a record is successfully written.

9. The computer-implemented method of claim 1 , wherein the echo read portion is 8 bytes.

10. The computer-implemented method of claim 1 , wherein the echo read portion is used to form a complete cache line prior to writing to a status area.

11. A system for synchronous input/output (I/O) cache line padding comprising a recipient control unit operatively connected to a server, the server comprising a processor and memory, and configured to:
receive, via the processor, at the recipient control unit, a partial cache line direct memory access (DMA) write request from the server;
fetch, via the processor, a device table entry (DTE) associated with the partial cache line DMA write request;
determine, via the processor, a cache line size for a synchronous I/O cache line;
determine, via the processor, whether a cache line padding bit in the DTE is set;
based on determining that the cache line padding bit in the DTE is set, writing a full cache line DMA write request by padding, via the processor, the partial cache line DMA write request with a padded portion, wherein the padded portion is based on an echo read portion and the cache line size; and
based on determining that the cache line padding bit in the DTE is not set, writing the partial cache line DMA write request.

12. The system of claim 11 , wherein the full cache line DMA write request comprises the partial cache line DMA write request and the padded portion.

13. The system of claim 11 , wherein the full cache line DMA write request is the same size as an address length boundary size.

14. The system of claim 11 , wherein the cache line size of the server is configured for 256 bytes of information.

15. The system of claim 11 , wherein the DMA write request comprises an 8 byte portion and the padded portion, wherein the padded portion is 248 bytes of information.

16. The system of claim 11 , wherein the padded portion consists of zeroes.

17. The system of claim 11 , wherein the server and the recipient control unit have different cache line sizes.

18. The system of claim 11 , wherein the echo read portion is a confirmation that a record is successfully written.

19. The system of claim 11 , wherein the echo read portion is 8 bytes.

20. The system of claim 11 , wherein the echo read portion is used to form a complete cache line prior to writing to a status area.

Assignees

• IBM

Inventors

• Brewer Scott A
• Craddock David F
• Kalos Matthew J
• Klein Matthias
• Lais Eric N

Classifications

• G06F2212/281

  Single cache · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F2213/28

  DMA · CPC title