Opportunistic migration of memory pages in a unified virtual memory system

Patent metadata

Field	Value
Publication number	US-10133677-B2
Application number	US-201314133489-A
Country	US
Kind code	B2
Filing date	Dec 18, 2013
Priority date	Mar 14, 2013
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency.

First claim

What is claimed is:

1. A computer-implemented method for transitioning a memory page between memories in a virtual memory subsystem, the method comprising:
detecting a first page fault in response to a first memory access request associated with a first memory page, wherein the first memory page resides at a first memory address in a system memory associated with a central processing unit (CPU), and a local page table does not include an entry corresponding to a virtual memory address included in the first memory access request; and
in response to the first page fault, executing a page fault sequence that includes:
modifying an ownership state of the first memory page to be a central-processing-unit-shared state, wherein, when in the central-processing-unit-shared state, both the CPU and a parallel processing unit (PPU) are able to access the first memory page at the first memory address in the system memory without experiencing a page fault; and
scheduling the first memory page for migration from the system memory associated with the CPU to a local memory associated with the PPU based on a history of at least one of the PPU and the CPU accessing the first memory page.

2. The method of claim 1 , further comprising:
associating a first page table entry in a page table associated with the PPU with the first memory page;
determining whether the first memory access request associated with the first page fault was a memory write operation; and
if the first memory access request associated with the first page fault was a memory write operation, then setting an access characteristic in the first page table entry to read/write, or
if the first memory access request associated with the first page fault was not a memory write operation, then setting an access characteristic in the first page table entry to read-only.

3. The method of claim 2 , further comprising:
setting an access characteristic in a second page table entry associated with the CPU to read-only; and
modifying the ownership state of the first memory page to be pending-migration.

4. The method of claim 2 , further comprising:
setting an access characteristic in a second page table entry associated with the CPU to invalid; and
modifying the ownership state of the first memory page to be pending-migration.

5. The method of claim 1 , wherein executing the page fault sequence further comprises:
determining that a use history associated with the first memory page indicates that the first memory page is likely to be accessed primarily by the PPU.

6. The method of claim 5 , further comprising:
updating a CPU page table to remove an entry corresponding to the virtual memory address and associating the virtual memory address with the first memory page; and
causing the first memory page to be transmitted from the system memory to the local memory associated with the PPU.

7. The method of claim 5 , further comprising:
determining that a second memory page is scheduled for migration from the system memory to the local memory associated with the PPU; and
causing the second memory page to migrate from the system memory to the local memory associated with the PPU in conjunction with causing the first memory page to migrate from the system memory to the local memory associated with the PPU.

8. The method of claim 7 , wherein each memory page in the local memory associated with the PPU is larger than each memory page in the system memory, and wherein both the first memory page and the second memory page are to be combined to form at least a portion of the larger third memory page stored in the local memory associated with the PPU.

9. The method of claim 1 , wherein executing the page fault sequence further comprises:
determining that usage history for the first memory page indicates that the first memory page is likely to be accessed by both the PPU and the CPU;
determining that a second memory page resides in the local memory associated with the PPU, wherein each memory page in the local memory associated with the PPU is larger than each memory page in the system memory, and wherein both the first memory page and a second memory page are associated with a first larger memory page; and
deferring the migration of the first memory page from the system memory to the local memory associated with the PPU.

10. The method of claim 1 , further comprising:
migrating the first memory page from the system memory associated with the CPU to the local memory associated with the PPU; and
modifying the ownership state of the first memory page to be a parallel-processing-unit-owned state.

11. The method of claim 1 , further comprising modifying the ownership state of the first memory page to be the central-processing-unit-shared state based on a frequency of accesses of the first memory page by the PPU.

12. A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to perform an operation for transitioning a memory page between memories in a virtual memory subsystem, the operation comprising:
detecting a first page fault in response to a first memory access request associated with a first memory page, wherein the first memory page resides at a first memory address in a system memory associated with a central processing unit (CPU), and a local page table does not include an entry corresponding to a virtual memory address included in the first memory access request; and
in response to the first page fault, executing a page fault sequence that includes:
modifying an ownership state of the first memory page to be a central-processing-unit-shared state, wherein, when in the central-processing-unit-shared state, both the CPU and a parallel processing unit (PPU) are able to access the first memory page at the first memory address in the system memory without experiencing a page fault; and
scheduling the first memory page for migration from the system memory associated with the CPU to a local memory associated with the PPU based on a history of at least one of the PPU and the CPU accessing the first memory page.

13. The non-transitory computer-readable storage medium of claim 12 , further comprising:
associating a first page table entry in a page table associated with the PPU with the first memory page;
determining whether the first memory access request associated with the first page fault was a memory write operation; and
if the first memory access request associated with the first page fault was a memory write operation, then setting an access characteristic in the first page table entry to read/write, or
if the first memory access request associated with the first page fault was not a memory write operation, then setting an access characteristic in the first page table entry to read-only.

14. The non-transitory computer-readable storage medium of claim 13 , further comprising:
setting an access characteristic in a second page table entry associated with the CPU to read-only; and
modifying the ownership state of the first memory page to be pending-migration.

15. The non-transitory computer-readable storage medium of claim 13 , further comprising:
setting an access characteristic in a second page table entry associated with the CPU to invalid; and
modifying the ownership state of the first memory page to be pending-migration.

16. The non-transitory computer-readable storage medium of claim 12 , wherein executing the page fault sequence further comprises:
determining that a use history associated with the first memory page indicates that the first me

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Buschardt Cameron
• Deming James Leroy
• Dunning Lucien
• Fahs Brian
• Hairgrove Mark
• Mashey John

Classifications

• G06F2212/251

  Local memory within processor subsystem · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F2212/301

  In special purpose processing node, e.g. vector processor · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/122 Primary

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title