Ring modulators with low-loss and large free spectral range (fsr) on a silicon-on-insulator (soi) platform
US-2024369864-A1 · Nov 7, 2024 · US
US10133098B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10133098-B2 |
| Application number | US-201514689601-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 17, 2015 |
| Priority date | Apr 18, 2014 |
| Publication date | Nov 20, 2018 |
| Grant date | Nov 20, 2018 |
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A metal-oxide semiconductor (MOS) optical modulator including a doped semiconductor layer having a waveguide structure, a dielectric layer disposed over the waveguide structure of the doped semiconductor layer, a gate region disposed over the dielectric layer, wherein the gate region comprises a transparent electrically conductive material having a refractive index lower than that of silicon, and a metal contact disposed over the gate region. The metal contact, the gate region, and the waveguide structure of the doped semiconductor layer may be vertically aligned with each other.
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What is claimed is: 1. A metal-oxide semiconductor (MOS) capacitor optical modulator, comprising: a doped semiconductor layer having a waveguide structure; a dielectric layer disposed over the waveguide structure of the doped semiconductor layer, wherein a first surface of the dielectric layer is coupled to the doped semiconductor layer having a waveguide structure; a gate region disposed directly above the dielectric layer and the waveguide structure of the doped semiconductor layer, wherein a second surface of the dielectric layer is coupled to the gate region, wherein the gate region comprises a transparent electrically conductive material having a refractive index lower than that of silicon, and wherein the gate region, the dielectric layer, the waveguide structure collectively form a waveguide of the MOS capacitor optical modulator, the doped semiconductor layer comprising at least two etched out portions positioned on opposite sides of the gate region, each of the etched out portions comprising sidewalls that are coplanar with sidewalls of the gate region; a metal contact disposed over the gate region, sidewalls of the metal contact being coplanar with the sidewalls of the gate region; and a cladding material covering the etched out portions, the sidewalls of the gate region, and the sidewalls of the metal contact. 2. The MOS capacitor optical modulator of claim 1 , wherein the metal contact, the gate region, and the waveguide structure of the doped semiconductor layer are vertically aligned with each other. 3. The MOS capacitor optical modulator of claim 1 , wherein the gate region is an n-doped zinc oxide (ZnO). 4. The MOS capacitor optical modulator of claim 1 , wherein the doped semiconductor layer is a p-doped silicon, and wherein the gate region is one of an n-doped zinc oxide (ZnO), an n-doped silicon carbide (SiC), and an n-doped indium tin oxide (ITO). 5. The MOS capacitor optical modulator of claim 1 , wherein the gate region is transparent in an optical telecommunications wavelength band between 1.3 micrometers (μm) and 1.55 μm. 6. The MOS capacitor optical modulator of claim 1 , wherein the cladding material is a silicon dioxide (SiO 2 ) cladding material, and wherein the refractive index of the gate region is higher than that of the SiO 2 cladding material. 7. The MOS capacitor optical modulator of claim 1 , wherein the dielectric layer is a gate oxide comprising one of silica and silicon nitride. 8. The MOS capacitor optical modulator of claim 1 , wherein the metal contact is disposed directly above the gate region. 9. The MOS capacitor optical modulator of claim 1 , wherein the doped semiconductor layer is an upper layer of a semiconductor-on-insulator (SOI) wafer. 10. A metal-oxide semiconductor (MOS) capacitor optical modulator, comprising: a semiconductor-on-insulator (SOI) wafer portion having an upper semiconductor layer disposed over a buried oxide formed on a semiconductor substrate, wherein the upper semiconductor layer includes a waveguide structure; a dielectric layer disposed over the waveguide structure of the upper semiconductor layer, wherein a first surface of the dielectric layer is coupled to the doped semiconductor layer having a waveguide structure; a gate region disposed directly above the dielectric layer and the waveguide structure of the upper semiconductor layer, wherein a second surface of the dielectric layer is coupled to the gate region, wherein the gate region comprises a transparent electrically conductive material having a refractive index lower than that of silicon, and wherein the gate region, the dielectric layer, the waveguide structure collectively form a waveguide of the MOS capacitor optical modulator, the doped semiconductor layer comprising at least two etched out portions positioned on opposite sides of the gate region, each of the etched out portions comprising sidewalls that are coplanar with sidewalls of the gate region; a metal contact disposed directly above the gate region and the waveguide structure of the upper semiconductor layer, sidewalls of the metal contact being coplanar with the sidewalls of the gate region; and a cladding material covering the etched out portions, the sidewalls of the gate region, and the sidewalls of the metal contact. 11. The MOS capacitor optical modulator of claim 10 , wherein the upper semiconductor layer is a p-doped silicon-containing material, and wherein the gate region is an n-doped zinc oxide (ZnO). 12. The MOS capacitor optical modulator of claim 10 , wherein the gate region is transparent in an optical telecommunications wavelength band between 1.3 micrometers (μm) and 1.55 μm. 13. The MOS capacitor optical modulator of claim 10 , wherein the cladding material is a silicon dioxide (SiO 2 ) cladding material, and wherein the refractive index of the gate region is higher than that of the SiO 2 cladding material. 14. The MOS capacitor optical modulator of claim 10 , wherein a doping concentration of the upper semiconductor layer proximate a source of the MOS capacitor optical modulator is less than a doping concentration of the upper semiconductor layer proximate a drain of the MOS capacitor optical modulator. 15. The MOS capacitor optical modulator of claim 10 , wherein a second metal contact is laterally spaced apart from the gate region by cladding material and disposed upon the upper semiconductor layer. 16. The MOS capacitor optical modulator of claim 10 , wherein the gate region and the buried oxide are physically separated by the upper semiconductor layer along an entire bottom surface of the gate region. 17. A method of forming a metal-oxide semiconductor (MOS) capacitor optical modulator, comprising: forming a waveguide structure in a semiconductor layer; forming a dielectric layer over the waveguide structure of the semiconductor layer, wherein a first surface of the dielectric layer is coupled to the doped semiconductor layer having a waveguide structure; depositing a gate region material directly above the dielectric layer and the waveguide structure of the semiconductor layer, wherein a second surface of the dielectric layer is coupled to the gate region, wherein the gate region material comprises a transparent electrically conductive material having a refractive index lower than that of silicon, wherein the gate region, the dielectric layer, and the waveguide structure collectively form a waveguide of the MOS capacitor optical modulator, the doped semiconductor layer comprising at least two etched out portions positioned on opposite sides of the gate region, each of the etched out portions comprising sidewalls that are coplanar with sidewalls of the gate region; forming a metal contact over the gate region material, sidewalls of the metal contact being coplanar with the sidewalls of the gate region; and depositing a cladding material to cover the etched out portions, the sidewalls of the gate region, and the sidewalls of the metal contact. 18. The method of claim 17 , further comprising vertically aligning the metal contact, the gate region material, and the waveguide structure of the semiconductor layer. 19. The method of claim 17 , further comprising depositing the gate region material by one of metal organic chemical vapor deposition (MOCVD), radio frequency (RF) sputtering, and plasma enhanced atomic layer deposition. 20. The method of claim 17 , further comprising etching the semiconductor layer to form the waveguide structure, and implanting the gate region material with a first dopant an
Silicon · CPC title
Modulator · CPC title
Integrated optical circuits characterised by the manufacturing method · CPC title
based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction (G02F1/03 takes precedence) · CPC title
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