Loss of signal detection on CDR

Patent metadata

Field	Value
Publication number	US-10129017-B1
Application number	US-201816028229-A
Country	US
Kind code	B1
Filing date	Jul 5, 2018
Priority date	Sep 1, 2015
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

The present invention is directed to data communication. More specifically, an embodiment of the present invention provides a technique for detecting loss of signal. An incoming data stream is sampled and a recovered clock signal is generated accordingly. An output clock signal of a higher frequency than the recovered clock signal is generated by a transmission PLL. The frequency of the recovered clock signal is compared to a divided frequency of the output clock signal. If a difference between the recovered clock signal and the output clock signal is greater than a threshold, a loss of signal indication is provided. There are other embodiments as well.

First claim

What is claimed is:

1. A loss-of signal detection device comprising:
an input terminal for processing an input data stream, the input data stream being characterized by a first data frequency;
a sampler configured to provide a sampled data stream by sampling the input data stream;
a first PLL configured to generate a recovered clock signal at a second data frequency, the first PLL being characterized by a first frequency range;
a second PLL configured to generate a transmission clock signal at a third data frequency by frequency multiplying using at least the recovered clock signal, the second PLL being characterized by a second frequency range, the second PLL generating an incorrect clock signal if the recovered clock signal is not stable, the second frequency range being smaller than the first frequency range, the third data frequency being greater than the second data frequency by a predetermined ratio, the predetermined ratio being determined based on a ratio between the third data frequency and the second data frequency; and
a detection module comprising a frequency divider and a frequency comparator, the frequency divider being configured to divide the transmission clock signal by the predetermined ratio, the frequency comparator being configured to determine whether a difference between the divided transmission clock signal and the recovered clock signal is greater than a predetermined threshold, the difference in a clock count being associated with the incorrect clock signal and the recovered clock signal, the detection module being configured to provide a loss of signal indication if the difference is greater than the predetermined threshold.

2. The device of claim 1 wherein the detection module comprises counters for store a number of duty cycles associated with the divided transmission clock signal and a number of duty cycles associated with the recovered clock signal within a predetermined time interval.

3. The device of claim 1 further comprising a phase detection module for processing the sampled data stream.

4. The device of claim 1 wherein the sampler comprises a data sense amplifier and an edge sense amplifier.

5. The device of claim 1 further comprising a transmission driver configured to transmit the sample data stream using the transmission clock signal.

6. The device of claim 1 further comprising an optical communication interface for transmitting the sample data stream at the third data frequency.

7. The device of claim 1 further comprising a CTLE module.

8. The device of claim 1 further comprising a phase detection logic.

9. The device of claim 1 wherein the first PLL provides the recovered clock signal to the sampler.

10. A method for lock detection, the method comprising:
determining a signal strength associated with an incoming data stream, the incoming data stream being characterized by a first frequency;
generating a recovered clock signal based on the incoming data stream using a first PLL if the signal strength is greater than a predetermined threshold strength, the recovered clock signal being characterized by a second frequency;
generating an output clock signal using a second PLL, the output clock signal being characterized by a third frequency, the third frequency being m times the frequency of the second frequency, the second PLL generating an incorrect clock signal if the recovered clock signal is not stable;
dividing the output clock signal by a factor of m;
determining a first edge count for the recovered clock signal during a predetermined time interval;
determining a second edge count for the divided output clock signal during the predetermined time interval, the second edge count being associated with potentially incorrect clock signal;
calculating a difference between the first edge count and the second edge count; and
generating a loss of signal indication if the difference is greater than a predetermined threshold count or if the signal strength is below the predetermined threshold strength.

11. The method of claim 10 further comprising performing phase detection on the sampled data.

12. The method of claim 10 further comprising transmitting the incoming data stream using the output clock signal at the third frequency.

13. The method of claim 10 further comprising sampling the incoming data.

14. The method of claim 10 further comprising equalizing the incoming data.

15. The method of claim 10 further comprising outputting a loss of signal indication during a second time interval if the difference is greater than the predetermined threshold.

16. A method for lock detection, the method comprising:
sampling an input data stream to provide a sample data stream;
determining a signal strength associated with the input data stream;
generating a recovered clock signal at a second data frequency using a first PLL, the first PLL being characterized by a first frequency range;
generating a transmission clock signal at a third frequency using at least the recovered clock signal using a second PLL, the second PLL being characterized by a second frequency range, the second frequency range being smaller than the first frequency range, the second PLL generating an incorrect clock signal if the input data stream is unstable, the third frequency being greater than the second data frequency by a predetermined ratio, the predetermined ratio being determined based on a ratio between the third frequency and the second frequency; and
generating a locking indication based on a first duty cycle of the recovered clock signal and a second duty cycle count of the transmission clock signal over a predetermined period of time, the locking indication being based on a difference between a first clock cycle count associated with the recovered clock signal and a second clock cycle count associated with the incorrect clock signal during the predetermined period of time.

17. The method of claim 16 wherein the sampling is performed by a sense amplifier.

18. The method of claim 16 wherein the second PLL comprises a PLL core and a detection module.

19. The method of claim 16 further comprising generating an output data characterized by the third frequency.

20. The method of claim 18 wherein the detection module comprises a divider module.

Assignees

• Inphi Corp

Inventors

• Mishra Parmanand
• Forey Simon

Classifications

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/0091

  Transmitter details · CPC title

• H03L7/00 Primary

  Automatic control of frequency or phase; Synchronisation · CPC title