Data processor, data processing method and communication device

Patent metadata

Field	Value
Publication number	US-10128818-B2
Application number	US-201715553909-A
Country	US
Kind code	B2
Filing date	Jan 16, 2017
Priority date	Mar 8, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A parallel transfer rate converter inputs first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputs second parallel data with number of samples being S2=S1×(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock. A convolution operation device inputs the second parallel data in synchronism with the second clock, generates third parallel data with number of samples being S3=S2×(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputs the third parallel data in synchronism with the second clock.

First claim

The invention claimed is:

1. A data processor converting a sampling rate to n/m times (n and m are integers equal to or larger than 1), comprising:
a parallel transfer rate converter inputting first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputting second parallel data with number of samples being S2=S1×(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock; and
a convolution operation device inputting the second parallel data in synchronism with the second clock, generating third parallel data with number of samples being S3=S2×(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputting the third parallel data in synchronism with the second clock.

2. The data processor according to claim 1 , wherein n times of S2 is a multiple of m.

3. The data processor according to claim 1 , wherein the convolution operation corresponds to processing of thinning by every m and executing a convolution operation of a filter coefficient and data interpolated by inserting (n−1) pieces of zero data between respective samples of the second parallel data.

4. The data processor according to claim 3 , wherein the filter coefficient is a finite impulse response.

5. The data processor according to claim 3 , wherein the filter coefficient is a filter coefficient for compensating transmission characteristics.

6. The data processor according to claim 1 , further comprising a compensation circuit compensating waveform distortion of the first parallel data, wherein n/m is larger than 1.

7. The data processor according to claim 1 , wherein each of S1 and S3 is a power of 2.

8. The data processor according to claim 1 , wherein S1=S3.

9. A communication device comprising:
a reception circuit receiving a transmission signal, converting the transmission signal to a reception signal and outputting the reception signal;
a sampling circuit sampling the reception signal;
a serial/parallel conversion circuit converting a sampled serial data to the first parallel data;
the data processor according to claim 1 ; and
a demodulation circuit demodulating an output signal of the convolution operation device and outputting a demodulation data.

10. A data processing method performed by a data processor converting a sampling rate to n/m times (n and m are integers equal to or larger than 1), comprising:
a step of inputting first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputting second parallel data with number of samples being S2=S1×(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock; and
a step of inputting the second parallel data in synchronism with the second clock, generating third parallel data with number of samples being S3=S2×(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputting the third parallel data in synchronism with the second clock.

Assignees

• Ntt Electronics Corp
• Nippon Telegraph & Telephone

Inventors

• Onuma Yasuharu
• Yamazaki Etsushi
• Takei Kazuhito
• Ishida Osamu
• Horikoshi Kengo
• Yoshida Mitsuteru
• Kisaka Yoshiaki
• Tomizawa Masahito

Classifications

• H04L7/0029

  interpolation of received data signal · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H03H2017/0214

  with input-sampling frequency and output-delivery frequency which differ, e.g. interpolation, extrapolation; anti-aliasing · CPC title

• H03H2017/0245

  Measures to reduce power consumption · CPC title

• H03H17/0227 Primary

  Measures concerning the coefficients · CPC title