Packaging methods and packaged semiconductor devices

Patent metadata

Field	Value
Publication number	US-10128175-B2
Application number	US-201313753328-A
Country	US
Kind code	B2
Filing date	Jan 29, 2013
Priority date	Jan 29, 2013
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

Packaging methods and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes forming first contact pads on a carrier, forming a wiring structure over the first contact pads, and forming second contact pads over the wiring structure. A first packaged semiconductor device is coupled to a first set of the second contact pads, and a second packaged semiconductor device is coupled to a second set of the second contact pads. The carrier is removed. The second packaged semiconductor device comprises a different package type than the first packaged semiconductor device.

First claim

What is claimed is:

1. A method of packaging semiconductor devices, the method comprising:
forming a plurality of first contact pads on a first seed layer disposed over a carrier;
forming a wiring structure over the plurality of first contact pads;
forming a second seed layer over and electrically coupled to the wiring structure;
forming a plurality of second contact pads over and electrically coupled to second seed layer, the second contact pads comprising a layer of solder and a layer of nickel overlying the layer of solder, the layer of nickel physically contacting both the layer of solder and the second seed layer, the layer of solder physically contacting the second seed layer, a lowermost surface of the second seed layer being lower than a lowermost surface of the layer of solder, and an uppermost surface of the second seed layer is higher than an uppermost surface of the layer of solder;
coupling a first packaged semiconductor device to a first set of the plurality of second contact pads;
coupling a second packaged semiconductor device to a second set of the plurality of second contact pads, the second packaged semiconductor device comprising a different package type than the first packaged semiconductor device, the second packaged semiconductor device comprising an integrated circuit;
encapsulating the first packaged semiconductor device, including a topmost surface of the first packaged semiconductor device, in a molding compound and partially encapsulating the second packaged semiconductor device in the molding compound, wherein a topmost surface of the second packaged semiconductor device is uncovered by the molding compound; and
removing the carrier and the first seed layer.

2. The method according to claim 1 , further comprising forming a conductive ball on each of the plurality of first contact pads.

3. The method according to claim 1 , further comprising after encapsulating the first packaged semiconductor device, reducing a thickness of the molding compound.

4. The method according to claim 1 , wherein forming the plurality of first contact pads comprises forming the first seed layer over the carrier, forming a first insulating material over the first seed layer, patterning the first insulating material, and plating a first conductive material on the first seed layer.

5. The method according to claim 4 , wherein forming the wiring structure comprises forming a redistribution layer (RDL).

6. The method according to claim 5 , wherein forming the RDL comprises forming a third seed layer over the patterned first insulating material and the first conductive material, plating a second conductive material over portions of the third seed layer, removing portions of the third seed layer, and forming a second insulating material over the first insulating material and the second conductive material.

7. The method according to claim 6 , wherein forming the plurality of second contact pads comprises forming the plurality of second contact pads over portions of the second conductive material.

8. A method of packaging semiconductor devices, the method comprising:
forming a first seed layer on a carrier;
forming a first insulating material over the first seed layer;
patterning the first insulating material to define a pattern for a plurality of first contact pads;
plating a first conductive material on the first seed layer to form the plurality of first contact pads;
forming a second seed layer over and physically contacting the first conductive material and the first insulating material;
forming a first layer of photoresist over the second seed layer;
patterning the first layer of photoresist to define a wiring structure;
plating a second conductive material on exposed portions of the second seed layer to forming the wiring structure, the wiring structure comprising:
a first portion extending through the first insulating material to the first plurality of contact pads; and
a second portion extending over a top surface of the first insulating material, wherein the plating the second conductive material is a single, continuous plating process to form the first and second portions of the wiring structure, a lowermost surface of a top surface of the wiring structure being higher than a topmost surface of the top surface of the first insulating material;

removing the first layer of photoresist;
forming a second insulating material over the second conductive material and the first insulating material;
patterning the second insulating material to define a pattern for a plurality of second contact pads;
forming a third seed layer over the patterned second insulating material and exposed portions of the second conductive material;
forming a second layer of photoresist over the third seed layer;
patterning the second layer of photoresist to further define the pattern for the plurality of second contact pads;
plating a third conductive material on exposed portions of the third seed layer to form the plurality of second contact pads, wherein plating the third conductive material comprises plating solder on the exposed third seed layer, a lowermost surface of the third seed layer is lower than a lowermost surface of the plated solder, and an uppermost surface of the third seed layer is higher than an uppermost surface of the plated solder;
coupling a first packaged semiconductor device to a first set of the plurality of second contact pads;
coupling a second packaged semiconductor device to a second set of the plurality of second contact pads, the second packaged semiconductor device comprising a different package type than the first packaged semiconductor device, the second packaged semiconductor device comprising a device type selected from the group consisting essentially of an integrated circuit, a plurality of integrated circuits, a system-in-a-package (SiP), an SiP module, a microelectromechanical system (MEMS), and combinations thereof, wherein coupling the first packaged semiconductor device and coupling the second packaged semiconductor device comprise reflowing the solder of the third conductive material;
encapsulating the first packaged semiconductor device and the second packaged semiconductor device in a molding compound, a topmost surface of the first packaged semiconductor device being covered by the molding compound and a topmost surface of the second packaged semiconductor device being uncovered by the molding compound;
removing the carrier and the first seed layer to expose the plurality of first contact pads; and
forming solder bumps on the exposed first contact pads.

9. The method according to claim 8 , further comprising coupling a plurality of the second packaged semiconductor devices to a plurality of second sets of the second contact pads, wherein each of the plurality of second packaged semiconductor devices comprises a heterogeneous package type with respect to others of the plurality of second packaged semiconductor devices.

10. The method according to claim 8 , wherein the first packaged semiconductor device comprises a device type selected from the group consisting essentially of an integrated circuit, a plurality of integrated circuits, a system-in-a-package (SiP), an SiP module, a discrete passive device, a microelectromechanical system (MEMS), a functional module, and combinations thereof.

11. The method according to claim 8 , wherein forming the first seed layer comprises forming Ti, wherein plating the first conductive material comprises plating Ni, wherein forming the second seed layer comprises forming TiCu, wherein plating the second conductive material comprises plating Cu, or wherein forming the third seed layer comprises forming TiCu.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Hung Jui-Pin

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07207

  Temporary substrates, e.g. removable substrates · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title