Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells

Patent metadata

Field	Value
Publication number	US-10128145-B2
Application number	US-201414220693-A
Country	US
Kind code	B2
Filing date	Mar 20, 2014
Priority date	Sep 11, 2012
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

Integrated circuits and manufacturing methods are presented for creating diffusion resistors ( 101, 103 ) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.

First claim

What is claimed is:

1. A method for forming an integrated circuit (IC), the method comprising:
providing a semiconductor substrate;
forming a first well by performing a plurality of successively deeper first implantations to implant first dopants of a first conductivity type in the semiconductor substrate with a deepest one of the first implantations having a first well depth at which a maximum concentration of said first dopants occurs, the first well depth being greater than or equal to an isolation depth of shallow trench isolation structures formed in the semiconductor substrate, the first well including a body region, and first and second regions disposed at opposite ends of the body region;
forming wells of the first conductivity type in a dual well CMOS process concurrently with the formation of the first well by performing the plurality of successively deeper first implantations;
forming a second well that laterally surrounds the first well by performing a plurality of successively deeper second implantations to implant second dopants of a second conductivity type with a deepest one of the second implantations having a second well depth at which a maximum concentration of said second dopants occurs, the second well depth being greater than or equal to the isolation depth, the second well being spaced from the first well in the semiconductor substrate by a lateral spacing distance, leaving a well-free portion of the semiconductor substrate extending laterally between the first and second wells, the semiconductor substrate having a dopant concentration lower than a dopant concentration of the second well and lower than a dopant concentration of the body region of the first well;
forming wells of the second conductivity type in the dual well CMOS process concurrently with the formation of the second well by performing the plurality of successively deeper second implantations; and
forming first and second contact structures individually connected to the first and second regions of the first well.

2. The method of claim 1 , wherein forming the first well comprises implanting dopants of the first conductivity type into the semiconductor substrate while covering the well-free portion of the semiconductor substrate with a first implant mask; and wherein forming the second well comprises implanting dopants of the second conductivity type into the semiconductor substrate while covering the well-free portion of the semiconductor substrate with a second implant mask.

3. The method of claim 2 , wherein the semiconductor substrate is P type; wherein forming the first well comprises implanting N type dopants into the semiconductor substrate; and wherein forming the second well comprises implanting P type dopants into the semiconductor substrate.

4. The method of claim 1 , comprising forming a deep well of the second conductivity type disposed in the semiconductor substrate to a depth greater than that of the first well; wherein the second well is formed between an upper surface of the semiconductor substrate and at least a portion of the deep well.

5. The method of claim 4 , wherein the semiconductor substrate is of the first conductivity type; wherein forming the deep well comprises implanting dopants of the second conductivity type into the semiconductor substrate; wherein forming the first well comprises implanting dopants of the first conductivity type into the semiconductor substrate; and wherein forming the second well comprises implanting dopants of the second conductivity type into the semiconductor substrate.

6. The method of claim 5 , wherein the first conductivity type is P type, and wherein the second conductivity type is N type.

7. The method of claim 1 , wherein the first well is formed to a depth of about 1.5 μm or less.

8. The method of claim 1 , wherein the lateral spacing distance is about 0.2 μm or more.

9. The method of claim 8 , wherein the lateral spacing distance is about 2.0 μm or less.

10. The method of claim 1 , wherein the lateral spacing distance is about 2.0 μm or less.

11. A method for forming an integrated circuit (IC), the method comprising:
providing a semiconductor substrate;
forming a first well with dopants of a first conductivity type in the semiconductor substrate, the first well including a body region, and first and second regions disposed at opposite ends of the body region;
forming a second well with dopants of a second conductivity type in the semiconductor substrate, the second well being spaced from the first well in the semiconductor substrate by a lateral spacing distance leaving a well-free portion of the semiconductor substrate extending laterally between the first and second wells, the semiconductor substrate having a dopant concentration lower than a dopant concentration of the second well and lower than a dopant concentration of the body region of the first well; and
forming first and second contact structures in the first well with dopants of the first conductivity type, the first and second contact structures individually connected to the first and second regions of the first well.

12. The method of claim 11 , wherein the a depth of the first well and a depth of the second well are both greater than or equal to an isolation depth of shallow trench isolation structures formed in the semiconductor substrate.

13. The method of claim 11 , wherein the substrate includes shallow trench isolation structures formed in the substrate, and wherein a depth of the first well and a depth of the second well are both greater than or equal to an isolation depth of the shallow trench isolation structures formed in the semiconductor substrate.

14. The method of claim 11 , wherein the substrate includes dopants of the second conductivity type.

15. The method of claim 14 , wherein the dopant concentration for the semiconductor substrate is a dopant concentration for dopants of the second conductivity type, the dopant concentration for the second well is a dopant concentration for dopants of the second conductivity type, and the dopant concentration for the body region of the first well is a dopant concentration for dopants of the first conductivity type.

16. The method of claim 1 , wherein the substrate includes dopants of the second conductivity type.

17. The method of claim 16 , wherein the dopant concentration for the semiconductor substrate is a dopant concentration for dopants of the second conductivity type, the dopant concentration for the second well is a dopant concentration for dopants of the second conductivity type, and the dopant concentration for the body region of the first well is a dopant concentration for dopants of the first conductivity type.

Assignees

• Texas Instruments Inc

Inventors

• Benaissa Kamel
• Chatterjee Amitava

Classifications

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10P30/22

  using masks · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30 Primary

  Isolation regions comprising PN junctions · CPC title

• H01L27/0629

  Electricity · mapped topic