Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-10128112-B2
Application number	US-201715595945-A
Country	US
Kind code	B2
Filing date	May 16, 2017
Priority date	Oct 5, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming a dummy gate electrode on a substrate;
forming a trench on a side surface of the dummy gate electrode;
performing a bake process of removing an impurity from the trench; and
forming a source/drain in the trench,
wherein the bake process comprises a first stage and a second stage following the first stage,
an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and
the bake process is performed while the substrate is disposed on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

2. The method of claim 1 , wherein the air pressure during the first stage is greater than the air pressure during the second stage.

3. The method of claim 1 , wherein the RPM of the substrate during the first stage is greater than the RPM of the substrate during the second stage.

4. The method of claim 1 , wherein the bake process comprises providing H 2 gas, and
a flowrate of the H 2 gas during the first stage is different from a flowrate of the H 2 gas during the second stage.

5. The method of claim 1 , wherein the first stage comprises a first sub-stage and a second sub-stage following the first sub-stage, and
the RPM of the substrate during the first sub-stage is different from the RPM of the substrate during the second sub-stage.

6. The method of claim 5 , wherein the RPM of the substrate during the first sub-stage is less than the RPM of the substrate during the second sub-stage.

7. The method of claim 1 , further comprising:
allowing an impurity on a surface of the trench to react with H during the first stage to thus form a product, and
allowing the product to be detached from the substrate during the second stage.

8. The method of claim 7 , wherein the product comprises at least one of O 2 , CH 4 and H 2 O.

9. The method of claim 7 , wherein the product comprises Si x C y O z , wherein x, y and z are natural numbers.

10. The method of claim 1 , wherein the bake process comprises:
a first cycle including the first stage and the second stage; and
a second cycle including a third stage and a fourth stage following the third stage,
wherein an air pressure in which the substrate is disposed during the third stage is different from an air pressure in which the substrate is disposed during the fourth stage.

11. The method of claim 10 , wherein a rotation direction of the substrate during the first cycle is different from a rotation direction of the substrate during the second cycle.

12. The method of claim 1 , wherein the bake process and the forming the source/drain are performed in-situ.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Cho Eun
• Kim Jin Bum
• Moon Kang Hun
• Choe Jae Myung
• Kim Sun Jung
• Shin Dong Suk
• Shin Il Gyou
• Yoo Jeong Ho

Classifications

• H10P70/273

  the processing being a delineation of conductive layers, e.g. by RIE · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10P14/3602 Primary

  In-situ cleaning · CPC title

• H01L21/223

  Electricity · mapped topic