Embedded substrate core spiral inductor

Patent metadata

Field	Value
Publication number	US-10128037-B2
Application number	US-201514753482-A
Country	US
Kind code	B2
Filing date	Jun 29, 2015
Priority date	Apr 10, 2015
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

Inductors are fabricated in core layers according to a predefined semiconductor package manufacturing process rules. The inductors provide an embedded substrate trace inductor solution. The inductors may be part of an on-chip voltage regulator or any other circuit design. The inductors provide a core spiral structure to help increase inductance, particularly using magnetic field coupling between inductors. The core layers provide thicker and heavier conductive segments for the inductors, particularly as compared to inductors fabricated in build-up layers according to the semiconductor package manufacturing process rules.

First claim

What is claimed is:

1. An inductor comprising:
a first conductive segment fabricated in a first core metal layer of a semiconductor package;
a second conductive segment fabricated in a second core metal layer of the semiconductor package;
a third conductive segment fabricated in the second core metal layer of the semiconductor package;
a first conductive core via through a core dielectric layer of the semiconductor package, the first conductive core via in contact with a first end of the first conductive segment and a first end of the second conductive segment;
a second conductive core via through the core dielectric layer of the semiconductor package, the second conductive core via in contact with a second end of the second conductive segment and a first end of the third conductive segment; and
an inductor terminal via connecting the first conductive segment to a fourth conductive segment within a build-up layer of the semiconductor package, wherein the first, the second, and the third conductive segments are fabricated with thicknesses that are greater than a thickness of the fourth conductive segment within the build-up layer.

2. The inductor of claim 1 , wherein the semiconductor package is fabricated using fabrication design rules that permit thicker lines in the core metal layers than in the build-up layer.

3. The inductor of claim 2 , where:
the fabrication design rules require greater pitch for metal lines in the core metal layers than in the build-up layer.

4. The inductor of claim 1 , where the first conductive segment comprises a horizontal displacement.

5. The inductor of claim 1 , where:
the first conductive segment is arranged to conduct current in a direction opposite the second conductive segment.

6. The inductor of claim 5 , where:
the first conductive segment comprises a horizontal displacement arranged to provide a horizontal offset for an additional conductive segment fabricated in the second core metal layer.

7. The inductor of claim 5 , where:
the second conductive segment comprises a horizontal displacement arranged to provide a horizontal offset for an additional conductive segment fabricated in the first core metal layer.

8. The inductor of claim 1 , further comprising
a common connection from the inductor terminal to at least one additional inductor terminal.

9. The inductor of claim 1 , where:
the first conductive segment, second conductive segment, and conductive core form a first turn of the inductor.

10. The inductor of claim 9 , further comprising:
a second turn of the inductor coupled to the first turn.

11. The inductor of claim 10 , where the second turn comprises:
a third conductive segment fabricated in the first core metal layer; and
a fourth conductive segment fabricated in the second core metal layer.

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Kim Namhoon
• Karikalan Sampath Komarapalayam
• Wang Zhihui
• Choi Jin Seong
• Tan Boon Leong
• Law Edward

Classifications

• H01F5/00

  Coils (superconducting coils H01F6/06; fixed inductances of the signal type H01F17/00) · CPC title

• H01F27/2804 Primary

  Printed windings · CPC title

• H01F27/29

  Terminals; Tapping arrangements {for signal inductances} · CPC title

• H01F2027/2809

  on stacked layers · CPC title