Supporting flow control mechanism of bus between semiconductor dies assembled in wafer-level package

Patent metadata

Field	Value
Publication number	US-10127169-B2
Application number	US-201615043622-A
Country	US
Kind code	B2
Filing date	Feb 15, 2016
Priority date	Feb 17, 2015
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.

First claim

What is claimed is:

1. A semiconductor die assembled in a wafer-level package, comprising:
a communication interface;
a bus master, coupled to a communication bus through the communication interface, wherein the bus master is arranged to communicate with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is further arranged to be controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus; and
a communication channel, for connecting the semiconductor die and the other semiconductor die, wherein the communication channel is a re-distribution layer (RDL) metal layer or a metal layer on the semiconductor dies.

2. The semiconductor die of claim 1 , wherein the wafer-level package is an integrated fan-out (InFO) package.

3. The semiconductor die of claim 1 , wherein the flow control mechanism is a back-pressure mechanism configured to generate a back-pressure signal from the bus slave to the bus master, and when the back-pressure signal is asserted, the bus master is blocked from issuing transaction over the communication bus.

4. The semiconductor die of claim 1 , wherein the flow control mechanism is a credit-based flow control mechanism configured to manage credit of the bus master, and when the credit fails to pass a predetermined criterion, the bus master is blocked from issuing transaction over the communication bus.

5. The semiconductor die of claim 4 , wherein the bus master is further arranged to update the credit when issuing new transaction over the communication bus.

6. The semiconductor die of claim 4 , wherein the bus master is further arranged to update the credit when receiving a credit update signal generated from the bus slave.

7. The semiconductor die of claim 1 , wherein the bus master is further arranged to support burst-based transactions.

8. The semiconductor die of claim 1 , wherein the bus master is further arranged to support multiple outstanding read/write transactions.

9. The semiconductor die of claim 1 , wherein the bus master is further arranged to support a peer-to-peer master/slave scheme.

10. The semiconductor die of claim 1 , wherein the bus master is further arranged to support atomic transactions.

11. A semiconductor die assembled in a wafer-level package, comprising:
a communication interface; and
a bus slave, coupled to a communication bus through the communication interface, wherein the bus slave is arranged to communicate with a bus master of another semiconductor die assembled in the wafer-level package via the communication bus, and is further arranged to trigger a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus; and
a communication channel, for connecting the semiconductor die and the other semiconductor die, wherein the communication channel is a re-distribution layer (RDL) metal layer or a metal layer on the semiconductor dies.

12. The semiconductor die of claim 11 , wherein the wafer-level package is an integrated fan-out (InFO) package.

13. The semiconductor die of claim 11 , wherein the bus slave comprises a queue arranged to buffer command and data included in the transaction flow initiated by the bus master over the communication bus; the flow control mechanism is a back-pressure mechanism; and the bus slave is arranged to trigger the back-pressure mechanism to assert a back-pressure signal transmitted to the bus master when a storage status of the queue satisfies a predetermined criterion.

14. The semiconductor die of claim 11 , wherein the flow control mechanism is a credit-based flow control mechanism configured to manage credit of the bus master; and the bus slave is arranged to trigger the credit-based flow control mechanism to assert a credit update signal generated to the bus master over the communication bus when transaction issued from the bus master has been executed by the bus slave.

15. The semiconductor die of claim 11 , wherein the bus slave is further arranged to support out-of-order transaction execution.

16. The semiconductor die of claim 11 , wherein the bus slave is further arranged to support a peer-to-peer master/slave scheme.

17. A wafer-level package comprising:
a communication bus;
a semiconductor die, comprising:
a plurality of bus masters, each arranged to be controlled by a flow control mechanism that manages a transaction flow over the communication bus; and
a bus arbiter, arranged to perform arbitration upon transaction requests issued from the bus masters and grant an access right of the communication bus to only one of the bus masters at a time, wherein the semiconductor die communicates with another semiconductor die in the wafer-level package via the communication bus; and

a communication channel, for connecting the semiconductor die and the other semiconductor die, wherein the communication channel is a re-distribution layer (RDL) metal layer or a metal layer on the semiconductor dies.

18. The wafer-level package of claim 17 , wherein the wafer-level package is an integrated fan-out (InFO) package.

19. A wafer-level package comprising:
a communication bus;
a semiconductor die, comprising:
a plurality of bus slaves, each arranged to trigger a flow control mechanism that manages a transaction flow over the communication bus; and
a bus dispatcher, arranged to dispatch the transaction flow from the communication bus to at least one of the bus slaves at a time, wherein the semiconductor die communicates with another semiconductor die in the wafer-level package via the communication bus; and

a communication channel, for connecting the semiconductor die and the other semiconductor die, wherein the communication channel is a re-distribution layer (RDL) metal layer or a metal layer on the semiconductor dies.

20. The wafer-level package of claim 19 , wherein the wafer-level package is an integrated fan-out (InFO) package.

Assignees

• Mediatek Inc
• Nephos Hefei Co Ltd

Inventors

• Su Yao-Chun

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title