Write suppression in non-volatile memory

Patent metadata

Field	Value
Publication number	US-10126958-B2
Application number	US-201514875160-A
Country	US
Kind code	B2
Filing date	Oct 5, 2015
Priority date	Oct 5, 2015
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

Techniques are disclosed for write suppression to improve endurance rating of non-volatile memories, such as QLC-NAND SSDs or other relatively slow, low endurance non-volatile memories. In an embodiment, an SSD is configured with a fast frontend non-volatile memory, a relatively slow lower endurance backend non-volatile memory, and a frontend manager that selectively transfers data from the fast memory to the slow memory based on transfer criteria. In operation, write data from the host is initially written to the fast memory by the frontend manager. The data is moved from the fast memory to the slow memory in bands. For each data band stored in the fast memory, the frontend manager tracks invalid data counts and data age. Only bands that still remain valid are transferred to the slow memory. After a given band has been fully transferred, it is erased and re-usable for other incoming writes by the frontend manager.

First claim

What is claimed is:

1. A method comprising:
receiving data to be written to a non-volatile memory;
writing the data to a fast non-volatile memory for storing one or more bands of data;
evaluating each of the bands of the fast non-volatile memory to identify one or more target bands for eviction from the fast non-volatile memory to a slow non-volatile memory having a lower durability rating than the fast non-volatile memory, wherein evaluating each of the bands of the fast non-volatile memory comprises:
determining a number of valid data blocks for each of the bands of the fast non-volatile memory;
determining an age of data of each of the bands of the fast non-volatile memory;
computing a merit score for each of the bands of the fast non-volatile memory based on a ratio of a number of invalid data blocks to the number of valid data blocks for each of the bands and further based on the age of the data for each of the bands, wherein any band having the merit score above a given eviction threshold is designated as a target band; and

moving valid data of the one or more target bands from the fast non-volatile memory to the slow non-volatile memory, wherein only valid data of the one or more target bands are moved from the fast non-volatile memory to the slow non-volatile memory.

2. The method of claim 1 wherein determining the number of valid blocks for each band comprises determining a number of valid logical block addresses (LBAs) for each band, and determining the age of the data of each band comprises determining how may bytes ago the LBA data was written.

3. The method of claim 1 wherein after moving the valid data of the one or more target bands from the fast non-volatile memory to the slow non-volatile memory, the method further comprises:
erasing the one or more target bands from the fast non-volatile memory.

4. The method of claim 1 , further comprising:
retaining specific logical block address (LBA) ranges in the fast non-volatile memory so as to eliminate need to duplicate the same content in the slow non-volatile memory.

5. A non-transitory computer program product comprising instructions encoded thereon that that when executed by one or more processors cause a process to be carried out, the process comprising:
receiving host data to be written to a solid-state storage device;
writing the host data to a fast non-volatile memory for storing one or more bands of data;
evaluating each of the bands of the fast non-volatile memory to identify one or more target bands for eviction from the fast non-volatile memory to a slow non-volatile memory having a lower durability rating than the fast non-volatile memory, wherein evaluating each of the bands of the fast non-volatile memory comprises:
determining a number of valid data blocks for each of the bands of the fast non-volatile memory;
determining an age of data of each of the bands of the fast non-volatile memory;
computing a merit score for each of the bands of the fast non-volatile memory based on a ratio of a number of invalid data blocks to the number of valid data blocks for each of the bands and further based on the age of the data for each of the bands, wherein any band having a score above a given eviction threshold is designated as a target band; and

moving valid data of the one or more target bands from the fast non-volatile memory to the slow non-volatile memory, wherein only valid data of the one or more target bands are moved from the fast to slow non-volatile memory.

6. The computer program product of claim 5 , the process further comprising at least one of:
temporarily buffering the host data prior to it being written to the fast non-volatile memory; and
acknowledging to the host that the write is complete prior to the host data being transferred to the slow non-volatile memory.

7. The computer program product of claim 5 wherein each band of data is associated with a plurality logical block addresses (LBAs), and moving valid data of the one or more target bands from the fast non-volatile memory to the slow non-volatile memory comprises moving valid LBAs from the fast non-volatile memory to the slow non-volatile memory, wherein only valid LBAs of the one or more target bands are moved from the fast to slow non-volatile memory.

8. The computer program product of claim 5 wherein determining the number of valid blocks for each band comprises determining a number of valid logical block addresses (LBAs) for each band, and determining the age of the data of each band comprises determining how may bytes ago the LBA data was written.

9. The computer program product of claim 5 wherein after moving the valid data of the one or more target bands from the fast non-volatile memory to the slow non-volatile memory, the process further comprises:
erasing the one or more target bands from the fast non-volatile memory.

10. The computer program product of claim 5 wherein evaluating each of the bands of the fast non-volatile memory to identify the one or more target bands for eviction from the fast non-volatile memory to a slow non-volatile memory comprises continuously monitoring the bands of the fast non-volatile memory independent of data being written.

11. The computer program product of claim 5 , further comprising:
retaining specific logical block address (LBA) ranges in the fast non-volatile memory so as to eliminate need to duplicate the same content in the slow non-volatile memory.

12. An apparatus comprising:
a host interface to receive data for storage; and
one or more controllers to facilitate write suppression, the one or more controllers configured to:
receive host data to be written to a non-volatile memory, the non-volatile memory including a fast non-volatile memory for storing one or more bands of data and a slow non-volatile memory having a lower durability rating than the fast non-volatile memory;
write the host data to the fast non-volatile memory;
evaluate each of the bands of the fast non-volatile memory to identify one or more target bands for eviction from the fast non-volatile memory to the slow non-volatile memory, wherein evaluating each of the bands of the fast non-volatile memory comprises:
determine a number of valid data blocks for each of the bands of the fast non-volatile memory;
determine an age of data of each of the bands of the fast non-volatile memory; and
compute a merit score for each of the bands of the fast non-volatile memory based on a ratio of a number of invalid data blocks to the number of valid data blocks for each of the bands and further based on the age of the data for each of the bands, wherein any band having the merit score above a given eviction threshold is designated as a target band; and

move valid data of the one or more target bands for eviction from the fast non-volatile memory to the slow non-volatile memory, wherein only valid data of the one or more target bands are moved from the fast to slow non-volatile memory.

13. The apparatus of claim 12 wherein each band of data is associated with a plurality logical block addresses (LBAs), and the one or more controllers are configured to move valid data blocks of the one or more target bands from the fast non-volatile memory to the slow non-volatile memory by moving valid LBAs from the fast non-volatile memory to the slow non-volatile memory, wherein only valid LBAs of the one or more target bands are moved from the fast to slow non-volatile memory.

14. The apparatus of claim 12 ,
wherein determining the number of valid blocks for each band comprises determining a number of valid logical block addresses (LBAs) for each band, and determining

Assignees

• Intel Corp

Inventors

• Ramalingam Anand S

Classifications

• G06F3/0647

  Migration mechanisms · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title