Low dropout voltage (LDO) regulator including a dual loop circuit and an application processor and a user device including the same

Patent metadata

Field	Value
Publication number	US-10126766-B2
Application number	US-201615216147-A
Country	US
Kind code	B2
Filing date	Jul 21, 2016
Priority date	Jan 26, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A low dropout voltage (LDO) regulator including: a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code; a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; and a fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal, wherein the coarse current and the fine current adjust a level of an output voltage.

First claim

What is claimed is:

1. A low dropout voltage (LDO) regulator, comprising:
a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code;
a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; and
a fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal,
wherein the coarse current and the fine current adjust a level of an output voltage,
wherein the coarse loop circuit has a current mirror circuit including MOS transistors, wherein the coarse loop circuit comprises:
a reference voltage changer configured to receive the coarse code and change a coarse reference voltage according to the coarse code;
an analog-to-digital converter (ADC) configured to receive the coarse reference voltage and the input voltage and generate the coarse code according to the coarse reference voltage and the input voltage; and
a coarse current driver configured to receive the coarse code and generate the coarse current according to the coarse code.

2. The LDO of claim 1 , further comprising a voltage divider configured to receive the output voltage to generate the input voltage.

3. The LDO of claim 1 , wherein the level of the output voltage is maintained in a steady state when the coarse loop circuit and the fine loop circuit operate at the same time.

4. The LDO of claim 1 , wherein the reference voltage generator is configured to increase the coarse reference voltage when a load current increases and decrease the coarse reference voltage when the load current decreases.

5. The LDO of claim 1 , wherein the reference voltage generator is configured to maintain a difference between the input voltage and the coarse reference voltage.

6. The LDO of claim 1 , wherein the coarse code includes a plurality of bits, wherein each bit is configured to turn on or off a corresponding transistor of the coarse current driver.

7. The LDO of claim 1 , wherein the ADC comprises the current mirror circuit and a comparator circuit configured to compare the input voltage with the coarse reference voltage, generate first and second currents according to the comparison result and provide the second current to a first node,
wherein the current minor circuit includes:
a first current mirror circuit configured to generate a third current that mirrors the first current and provide the third current to a second node; and
a second current mirror circuit configured to generate a bit of the coarse code according to a current difference between the first and second nodes.

8. The LDO of claim 7 , wherein the second current mirror circuit includes the MOS transistors, the MOS transistors including: a plurality of PMOS transistors and a plurality of corresponding NMOS transistors, wherein when a current value at a node of an NMOS transistor is greater than a current value at a node of a corresponding PMOS transistor, a bit value of the coarse code is a first level, and when the current value at the node of the NMOS transistor is less than the current value at the node of the corresponding PMOS transistor, the bit value of the coarse code is a second level.

9. The LDO of claim 8 , wherein when the first level is 0 the second level is 1, and when the first level is 1 the second level is 0.

10. The LDO of claim 1 , wherein the fine loop circuit comprises:
a comparator configured to compare the input voltage with a reference voltage and output a comparison result;
a shift register configured to receive the comparison result and the fine loop control signal and generate a fine code according to the comparison result and fine loop control signal; and
a fine current driver configured to generate the fine current according to the fine loop control signal.

11. The LDO of claim 10 , wherein the fine code includes a plurality of bits, each bit configured to turn on or off a corresponding transistor of the fine current driver.

12. The LDO of claim 10 , wherein the fine loop control signal includes an enable signal for activating the shift register, a disable signal for disabling the shift register and an initialization signal for determining an initial fine current.

13. The LDO of claim 12 , wherein the digital controller includes a plurality of control units and a logic gate, wherein each of the control units is configured to receive a corresponding bit of the coarse code and generate a plurality of control signals, and wherein the logic gate is configured to generate the fine loop control signal according to the plurality of control signals output from each of the control units.

14. The LDO of claim 13 , wherein the logic gate includes an OR gate.

15. The LDO of claim 13 , wherein a first control unit of the control units comprises:
an enable fine loop controller including a 4-bit counter and a rising edge detector, the 4-bit counter is configured to receive a first bit of the coarse code and provide a first output value to the rising edge detector and provide a fourth output value as a first enable signal, and the rising edge detector is configured to detect a rising edge of the first output value and output a first disable signal; and
an initial fine current selector including a 3-bit counter and a logic circuit, the 3-bit counter is configured to receive a third output value of the 4-bit counter and generate a 3-bit output, and the logic circuit is configured to receive the 3-bit output and generate first initialization signals.

16. A low dropout voltage (LDO) regulator, comprising:
an output voltage node;
a voltage divider connected to the output voltage node and configured to receive an output voltage that is adjusted in response to a fine current and a coarse current, and to divide the output voltage to generate an input voltage;
a coarse loop circuit configured to generate a coarse code in response to the input voltage and generate the coarse current in response to the coarse code;
a fine loop circuit configured to generate a fine code in response to the input voltage and a plurality of fine control signals and to generate the fine current in response to the fine code; and
a digital controller configured to generate the plurality of fine control signals in response to the coarse code,
wherein the coarse loop circuit has a current mirror circuit including MOS transistors,
wherein the coarse loop circuit includes a reference voltage changer that maintains a coarse reference voltage when the output voltage is decreased at a first time, increases the coarse reference voltage when the output voltage is decreased at a second time, increases the coarse reference voltage when the output voltage increases at a third time, and maintains a difference between the coarse reference voltage and the output voltage at a fourth time.

17. The LDO of claim 16 , wherein the coarse loop circuit includes a plurality of PMOS transistors to supply the coarse current.

18. The LDO of claim 16 , wherein the fine loop circuit includes a plurality of MOS transistors to supply the fine current.

19. The LDO of claim 16 , wherein the plurality of fine control signals include an enable signal for activating the fine loop circuit, a disable signal for deactivating the fine loop circuit and an initialization code for determining an initial fine current.

20. The LDO of claim 16 , wherein the fine control signals are in

Assignees

• Samsung Electronics Co Ltd
• Korea Advanced Inst Sci & Tech

Inventors

• Cho Gyu-Hyeong
• Lee Yongjin
• Kim Dae-Yong
• Kim Sangho

Classifications

• H03K21/026

  comprising logic circuits · CPC title

• H03K5/1534

  Transition or edge detectors · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G05F1/561 Primary

  Voltage to current converters (amplifiers H03F) · CPC title