Semiconductor device

Patent metadata

Field	Value
Publication number	US-10123443-B2
Application number	US-201514930565-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Dec 25, 2014
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A semiconductor device including: a plurality of semiconductor units each constituting a three-level inverter circuit; and a connection unit electrically connecting the plurality of semiconductor units in parallel, wherein each of the semiconductor units includes: a multi-layer substrate including an insulating plate and circuit plates disposed on a primary surface of the insulating plate; a plurality of semiconductor elements each having a back surface thereof fixed to one of the circuit plates and a front surface thereof having primary electrodes; and wiring members electrically connected to the primary electrodes of the semiconductor elements, and wherein in each of the semiconductor units, the multi-layer substrate, the plurality of semiconductor elements, and the wiring members are configured in such a way as to constitute the three-level inverter circuit.

First claim

What is claimed is:

1. A semiconductor device for use in a single phase U of a three-phase inverter, comprising:
a plurality of semiconductor units, each of the semiconductor units being a separate three-level inverter circuit of a single-phase bride connection having a plurality of terminals that includes a P terminal, an M terminal, an N terminal, and a U terminal of the single-phase bridge connection; and
a connection unit electrically connecting the plurality of semiconductor units in parallel,
wherein each of said semiconductor units includes:
a multi-layer substrate including an insulating plate and circuit plates disposed on a primary surface of said insulating plate;
a plurality of semiconductor elements each having a back surface thereof fixed to one of said circuit plates and a front surface thereof having primary electrodes; and
wiring members electrically connected to the primary electrodes of said semiconductor elements, and

wherein in each of said semiconductor units, said multi-layer substrate, the plurality of semiconductor elements, and said wiring members are configured in such a way as to constitute said separate three-level inverter circuit of the single-phase bridge connection,
wherein the plurality of semiconductor units are disposed side-by-side on a same plane, and
wherein said connection unit is disposed above the plurality of semiconductor units and has a plurality of external terminals that include a P terminal, a M terminal, an N terminal, and a U terminal on a top surface thereof, each of the P, M, N and U terminals on the top surface connecting corresponding ones of the P, M, N, and U terminals of the three-level inverter circuits, respectively, in parallel.

2. The semiconductor device according to claim 1 , wherein said wiring members include a printed circuit board arranged facing towards the primary surface of said insulating plate of said multi-layer substrate, and a plurality of conductive posts electrically connecting said printed circuit board to at least some of said primary electrodes of each of said semiconductor elements.

3. The semiconductor device according to claim 2 ,
wherein each of said semiconductor units further comprises a plurality of primary terminal posts, as at least some of the plurality of terminals of the three-inverter circuit, each having a bottom end thereof fixed to one of said circuit plates of said multi-layer substrate and another end thereof protruding in a same direction through a through-hole in said printed circuit board, and
wherein said another end of each of the plurality of primary terminal posts is inserted into said connection unit thereby electrically connecting said plurality of semiconductor units in parallel via said connection unit.

4. The semiconductor device according to claim 2 , wherein said connection unit is a bus bar or a printed circuit board differing from said printed circuit board of said wiring members.

5. The semiconductor device according to claim 2 , wherein said semiconductor elements, said printed circuit board, and said conductive posts are sealed in each of said semiconductor units with a thermosetting resin.

6. The semiconductor device according to claim 1 , further comprising a case that houses the plurality of semiconductor units.

7. The semiconductor device according to claim 1 , wherein each of said semiconductor elements has on a back surface a collector electrode electrically connected to said circuit plate.

8. The semiconductor device according to claim 1 , wherein said wiring members include a plurality of wires electrically connected to said primary electrodes of said semiconductor elements.

9. The semiconductor device according to claim 1 , wherein said semiconductor units are arranged according to losses during an operation of said the semiconductor device in the respective semiconductor units such that said semiconductor elements that generate heat are spatially dispersed.

10. The semiconductor device according to claim 9 , wherein said semiconductor units are arranged such that said semiconductor elements at which said losses are greatest are on an outer side of said semiconductor device.

11. The semiconductor device according to claim 9 , wherein in each of the semiconductor units, said semiconductor elements are arranged such that said semiconductor elements in the plurality of semiconductor units that generate heat are disposed on an outer side of the semiconductor device.

Assignees

• Fuji Electric Co Ltd

Inventors

• Nakamura Hideyo
• Yamada Ryuji
• Takubo Hiromu

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title