Image processing apparatus including circuit configuration and method of controlling the same

Patent metadata

Field	Value
Publication number	US-10122883-B2
Application number	US-201515119803-A
Country	US
Kind code	B2
Filing date	Mar 31, 2015
Priority date	Apr 8, 2014
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

An image processing apparatus specifies a difference between a circuit configuration for processing an accepted job and a circuit configuration configured in a reconfiguration circuit, and based on the difference, selects a functional block to be reconfigured in the reconfiguration circuit, and reconfigures the reconfiguration circuit by reading configuration data from storage unit.

First claim

The invention claimed is:

1. An image processing apparatus, comprising:
a partially reconfigurable device on which logic circuitry providing one or more image processing functions can be created and which can replace only a part of the logic circuitry with another logic circuitry;
at least one processor which functions as:
an accepting unit configured to accept an image processing job which is executed using predetermined image processing functions provided by logic circuitry created on the partially reconfigurable device;
a reconfiguration unit configured to cause the partially reconfigurable device to create, on the partially reconfigurable device, new logic circuitry providing at least one image processing function which is included in the predetermined image processing functions necessary for executing the accepted job and is not provided by current logic circuitry being on the partially reconfigurable device, with a part of the current logic circuitry which provides another image processing function included in the predetermined image processing functions kept on the partially reconfigurable device; and
an execution unit configured to execute the accepted image processing job using both (i) the new logic circuitry which has been created on the partially reconfigurable device and provides the at least one image processing function and (ii) the part of the current logic circuitry which has been kept on the partially reconfigurable device and provide the another image processing function.

2. The image processing apparatus according to claim 1 ,
wherein the at least one processor further functions as a determination unit configured to determine whether or not there is a constraint condition for when the partially reconfigurable device is reconfigured,
wherein the reconfiguration unit,
in accordance with the constraint condition determined by the determination unit, determines configuration data to use for a reconfiguration.

3. The image processing apparatus according to claim 2 , wherein the constraint condition is a condition related to at least one of a circuit scale of the reconfiguration circuit, and a rewrite count.

4. The image processing apparatus according to claim 3 , wherein the reconfiguration unit determines the configuration data to use for the reconfiguration in accordance with a processing format of data used in a functional block included in the circuit configuration for processing the job.

5. The image processing apparatus according to claim 1 , wherein the at least one processor further functions as a selection unit configured to select the at least one image processing function, in accordance with a difference between the predetermined image processing functions necessary for executing the accepted job and one or more image processing functions provided by the current logic circuitry being on the partially reconfigurable device, wherein the difference includes a difference of a processing format of image data handled in each image processing function.

6. The image processing apparatus according to claim 5 , wherein
the processing format is a line processing format for handling image data in a line form, a rectangle processing format for handling image data in a rectangular form, or a linear processing format for handling compressed image data.

7. The image processing apparatus according to claim 1 , further comprising:
a storage for storing circuit configuration data predicted for an initial job that is executed after a power supply activation or after a return from sleep, and
the reconfiguration unit, after the power supply activation or after the return from sleep, reconfigures the partially reconfigurable device by reading the predicted configuration data from the storage prior to accepting a job.

8. The image processing apparatus according to claim 1 , further comprising a storage storing a plurality of pieces of circuit configuration data, the plurality of pieces of circuit configuration data corresponding respectively to different image processing functions, and
wherein the reconfiguration unit is further configured to identify the at least one image processing function, and
wherein the partially reconfigurable device obtains, from among the plurality pieces of circuit configuration data, at least one piece of circuit configuration data corresponding to the at least one image processing function identified by the reconfiguration unit and create the new logic circuitry based on the obtained piece of circuit configuration data.

9. The image processing apparatus according to claim 1 , wherein the circuit configuration data is data that is reconfigurable in finer processing units than the functional blocks.

10. The image processing apparatus according to claim 1 , wherein the partially reconfigurable device does not create, for executing the accepted image processing job, logic circuitry which provides the another image processing function on the partially reconfigurable device.

11. An image processing method comprising:
at least one processor which functions as:
accepting an image processing job which is executed using predetermined image processing functions provided by logic circuitry created on a partially reconfigurable device, wherein the partially reconfigurable device on which logic circuitry providing one or more image processing functions can be created and which can replace only a part of the logic circuitry with another logic circuitry;
making, on the partially reconfigurable device, new logic circuitry providing at least one image processing function which is included in the predetermined image processing functions necessary for executing the accepted job and is not provided by current logic circuitry being on the partially reconfigurable device, with a part of the current logic circuitry which provides another image processing function included in the predetermined image processing functions kept on the partially reconfigurable device; and
executing the accepted image processing job using both (i) the new logic circuitry which has been created on the partially reconfigurable device and provides the at least one image processing function and (ii) the part of the current logic circuitry which has been kept on the partially reconfigurable device and provide the another image processing function.

12. The image processing method according to claim 11 , further comprising: selecting the at least one image processing function, in accordance with a difference between the predetermined image processing functions necessary for executing the accepted job and one or more image processing functions provided by the current logic circuitry being on the partially reconfigurable device, wherein the difference includes a difference of a processing format of image data handled in each image processing function.

13. The image processing method according to claim 12 , wherein the processing format is a line processing format for handling image data in a line form, a rectangle processing format for handling image data in a rectangular form, or a linear processing format for handling compressed image data.

14. The image processing method according to claim 11 , further comprising avoiding making, for executing the accepted image processing job, logic circuitry which provides the another image processing function on the partially reconfigurable device.

15. An image processing apparatus comprising:
a partially reconfigurable device on which logic circuitry providing an image processing function can be created with another logic circuitry left on the partially reconfigurable device;
one or more c

Assignees

• Canon Kk

Inventors

• Yamamoto Naohiro

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• H04N2201/0094

  Multifunctional device, i.e. a device capable of all of reading, reproducing, copying, facsimile transception, file transception · CPC title

• H03K19/1776

  for memories · CPC title

• H04N1/32122

  in a separate device, e.g. in a memory or on a display separate from image data · CPC title

• H03K19/17748

  Structural details of configuration resources · CPC title